diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs
index 18bd98e..a8a9c12 100644
--- a/src/Language/SystemVerilog/AST/Expr.hs
+++ b/src/Language/SystemVerilog/AST/Expr.hs
@@ -61,7 +61,7 @@ data Expr
     | Inside  Expr [Expr]
     | MinTypMax Expr Expr Expr
     | Nil
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show Expr where
     show (Nil          ) = ""
@@ -125,7 +125,7 @@ instance Show Expr where
 
 data Args
     = Args [Expr] [(Identifier, Expr)]
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show Args where
     show (Args pnArgs kwArgs) = '(' : commas strs ++ ")"
@@ -137,7 +137,7 @@ data PartSelectMode
     = NonIndexed
     | IndexedPlus
     | IndexedMinus
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show PartSelectMode where
     show NonIndexed   = ":"
@@ -148,7 +148,7 @@ data DimsFn
     = FnBits
     | FnDimensions
     | FnUnpackedDimensions
-    deriving (Eq, Ord)
+    deriving Eq
 
 data DimFn
     = FnLeft
@@ -157,7 +157,7 @@ data DimFn
     | FnHigh
     | FnIncrement
     | FnSize
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show DimsFn where
     show FnBits               = "$bits"
diff --git a/src/Language/SystemVerilog/AST/Number.hs b/src/Language/SystemVerilog/AST/Number.hs
index 25fba23..ee8d605 100644
--- a/src/Language/SystemVerilog/AST/Number.hs
+++ b/src/Language/SystemVerilog/AST/Number.hs
@@ -156,7 +156,7 @@ data Bit
     | Bit1
     | BitX
     | BitZ
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show Bit where
     show Bit0 = "0"
@@ -186,7 +186,7 @@ data Number
     = UnbasedUnsized Bit
     | Decimal Int Bool Integer
     | Based   Int Bool Base Integer Integer
-    deriving (Eq, Ord)
+    deriving Eq
 
 baseSize :: Integral a => Base -> a
 baseSize Binary = 2
diff --git a/src/Language/SystemVerilog/AST/Op.hs b/src/Language/SystemVerilog/AST/Op.hs
index 5c4c6ca..774e349 100644
--- a/src/Language/SystemVerilog/AST/Op.hs
+++ b/src/Language/SystemVerilog/AST/Op.hs
@@ -23,7 +23,7 @@ data UniOp
     | RedNor
     | RedXor
     | RedXnor
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show UniOp where
     show LogNot  = "!"
@@ -66,7 +66,7 @@ data BinOp
     | Le
     | Gt
     | Ge
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show BinOp where
     show LogAnd  = "&&"
@@ -112,7 +112,7 @@ instance Show AsgnOp where
 data StreamOp
     = StreamL
     | StreamR
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show StreamOp where
     show StreamL  = "<<"
diff --git a/src/Language/SystemVerilog/AST/Type.hs b/src/Language/SystemVerilog/AST/Type.hs
index 1ee0572..3c2ecb2 100644
--- a/src/Language/SystemVerilog/AST/Type.hs
+++ b/src/Language/SystemVerilog/AST/Type.hs
@@ -51,7 +51,7 @@ data Type
     | TypeOf Expr
     | TypedefRef Expr
     | UnpackedType Type [Range] -- used internally
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show Type where
     show (Alias         xx    rs) = printf "%s%s" xx (showRanges rs)
@@ -140,7 +140,7 @@ data Signing
     = Unspecified
     | Signed
     | Unsigned
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show Signing where
     show Unspecified = ""
@@ -160,12 +160,12 @@ data NetType
     | TWire
     | TWand
     | TWor
-    deriving (Eq, Ord)
+    deriving Eq
 data IntegerVectorType
     = TBit
     | TLogic
     | TReg
-    deriving (Eq, Ord)
+    deriving Eq
 data IntegerAtomType
     = TByte
     | TShortint
@@ -173,14 +173,14 @@ data IntegerAtomType
     | TLongint
     | TInteger
     | TTime
-    deriving (Eq, Ord)
+    deriving Eq
 data NonIntegerType
     = TShortreal
     | TReal
     | TRealtime
     | TString
     | TEvent
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show NetType where
     show TSupply0   = "supply0"
@@ -216,7 +216,7 @@ instance Show NonIntegerType where
 data Packing
     = Unpacked
     | Packed Signing
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show Packing where
     show (Unpacked) = ""
diff --git a/src/Language/SystemVerilog/AST/Type.hs-boot b/src/Language/SystemVerilog/AST/Type.hs-boot
index 63b0165..40d9a77 100644
--- a/src/Language/SystemVerilog/AST/Type.hs-boot
+++ b/src/Language/SystemVerilog/AST/Type.hs-boot
@@ -7,5 +7,4 @@ type Identifier = String
 
 data Type
 instance Eq Type
-instance Ord Type
 instance Show Type