diff --git a/src/Convert/Logic.hs b/src/Convert/Logic.hs
index 3cc71ec..925964f 100644
--- a/src/Convert/Logic.hs
+++ b/src/Convert/Logic.hs
@@ -115,7 +115,8 @@ traverseModuleItem ports scopes =
                     , AlwaysC AlwaysComb $ Asgn AsgnOpEq Nothing lhs (Ident x)
                     ]
             where
-                t = TypeOf expr
+                t = Net (NetType TWire) Unspecified
+                        [(DimsFn FnBits $ Right expr, RawNum 1)]
                 x = "sv2v_tmp_" ++ shortHash (lhs, expr)
         -- rewrite port bindings to use temporary nets where necessary
         fixModuleItem (Instance moduleName params instanceName rs bindings) =
diff --git a/test/basic/wire_reg.sv b/test/basic/wire_reg.sv
new file mode 100644
index 0000000..294ef74
--- /dev/null
+++ b/test/basic/wire_reg.sv
@@ -0,0 +1,14 @@
+module top(inp, out);
+    input wire inp;
+    reg data;
+    always @* data = inp;
+    output logic [1:0] out;
+
+    parameter ON = 1;
+    generate
+        if (ON) begin : blk
+            assign out[0] = data;
+            always @* out[1] = data;
+        end
+    endgenerate
+endmodule
diff --git a/test/basic/wire_reg.v b/test/basic/wire_reg.v
new file mode 100644
index 0000000..d324cdb
--- /dev/null
+++ b/test/basic/wire_reg.v
@@ -0,0 +1,14 @@
+module top(inp, out);
+    input wire inp;
+    reg data;
+    always @* data = inp;
+    output reg [1:0] out;
+
+    parameter ON = 1;
+    generate
+        if (ON) begin : blk
+            always @* out[0] = data;
+            always @* out[1] = data;
+        end
+    endgenerate
+endmodule