diff --git a/Language/SystemVerilog/AST.hs b/Language/SystemVerilog/AST.hs
index ab7b6da..2777acf 100644
--- a/Language/SystemVerilog/AST.hs
+++ b/Language/SystemVerilog/AST.hs
@@ -77,7 +77,7 @@ data ModuleItem
   | Parameter  (Maybe Range) Identifier Expr
   | Localparam (Maybe Range) Identifier Expr
   | PortDecl   Direction (Maybe Range) Identifier
-  | LocalNet   Type Identifier (Maybe Expr)
+  | LocalNet   Type Identifier (Either [Range] (Maybe Expr))
   | Integer    [Identifier]
   | Always     (Maybe Sense) Stmt
   | Assign     LHS Expr
@@ -92,12 +92,13 @@ instance Show ModuleItem where
     Parameter  r n e -> printf "parameter %s%s = %s;"  (showRange r) n (showExprConst e)
     Localparam r n e -> printf "localparam %s%s = %s;" (showRange r) n (showExprConst e)
     PortDecl   d r x -> printf "%s %s%s;" (show d) (showRange r) x
-    LocalNet   t x v -> printf "%s%s%s;" (show t) x assignment
+    LocalNet   t x v -> printf "%s%s%s;" (show t) x extra
       where
-        assignment =
-          if v == Nothing
-            then ""
-            else " = " ++ show (fromJust v)
+        extra =
+          case v of
+            Left ranges -> (intercalate "\b" $ map (showRange . Just) ranges) ++ "\b"
+            Right Nothing -> ""
+            Right (Just val) -> " = " ++ show val
     Integer      a   -> printf "integer %s;"  $ commas a
     Always     Nothing  b -> printf "always\n%s" $ indent $ show b
     Always     (Just a) b -> printf "always @(%s)\n%s" (show a) $ indent $ show b
diff --git a/Language/SystemVerilog/Parser/Parse.y b/Language/SystemVerilog/Parser/Parse.y
index 5f6d17d..b71411b 100644
--- a/Language/SystemVerilog/Parser/Parse.y
+++ b/Language/SystemVerilog/Parser/Parse.y
@@ -214,8 +214,8 @@ ModuleItem :: { [ModuleItem] }
 : "parameter"  MaybeRange DeclAsgns ";"                 { map (uncurry $ Parameter  $2) $3 }
 | "localparam" MaybeRange DeclAsgns ";"                 { map (uncurry $ Localparam $2) $3 }
 | PortDecl(";")                                         { $1 }
-| "reg"    MaybeRange WireDeclarations ";"               { map (uncurry $ LocalNet $ Reg  $2) $3 }
-| "wire"   MaybeRange WireDeclarations ";"              { map (uncurry $ LocalNet $ Wire $2) $3 }
+| "reg"    MaybeRange VariableIdentifiers ";"           { map (uncurry $ LocalNet $ Reg  $2) $3 }
+| "wire"   MaybeRange VariableIdentifiers ";"           { map (uncurry $ LocalNet $ Wire $2) $3 }
 | "integer" Identifiers ";"                             { [Integer $2] }
 | "assign" LHS "=" Expr ";"                             { [Assign $2 $4] }
 | "always"                   Stmt                       { [Always Nothing $2] }
@@ -225,6 +225,18 @@ ModuleItem :: { [ModuleItem] }
 | "always" "@*"              Stmt                       { [Always (Just SenseStar) $3] }
 | Identifier ParameterBindings Identifier Bindings ";"  { [Instance $1 $2 $3 $4] }
 
+VariableIdentifiers :: { [(Identifier, Either [Range] (Maybe Expr))] }
+  : VariableType                         { [$1] }
+  | VariableIdentifiers "," VariableType { $1 ++ [$3] }
+VariableType :: { (Identifier, Either [Range] (Maybe Expr)) }
+  : Identifier            { ($1, Right $ Nothing) }
+  | Identifier "=" Expr   { ($1, Right $ Just $3) }
+  | Identifier Dimensions { ($1, Left $2) }
+
+Dimensions :: { [Range] }
+  : Range            { [$1] }
+  | Dimensions Range { $1 ++ [$2] }
+
 DeclAsgns :: { [(Identifier, Expr)] }
   : DeclAsgn               { [$1] }
   | DeclAsgn "," DeclAsgns { $1 : $3 }
@@ -423,7 +435,7 @@ portDeclToModuleItems dir (Just tf) mr l =
   where
     toItems (x, e) =
       [ PortDecl dir mr x
-      , LocalNet (tf mr) x e ]
+      , LocalNet (tf mr) x (Right e) ]
 
 getPortNames :: [ModuleItem] -> [Identifier]
 getPortNames items =