From 7e37fe4338e7f5b1a2870d12478edb1f15c9ed9a Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Thu, 28 Mar 2019 18:04:28 -0400 Subject: [PATCH] fix nested conditional preprocessor directives --- src/Language/SystemVerilog/Parser/Preprocess.hs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Language/SystemVerilog/Parser/Preprocess.hs b/src/Language/SystemVerilog/Parser/Preprocess.hs index 69828df..d1b8158 100644 --- a/src/Language/SystemVerilog/Parser/Preprocess.hs +++ b/src/Language/SystemVerilog/Parser/Preprocess.hs @@ -21,7 +21,7 @@ isNewline :: Token -> Bool isNewline (Token t _ _) = t == Spe_Newline unskippableDirectives :: [String] -unskippableDirectives = ["else", "elsif", "endif"] +unskippableDirectives = ["else", "elsif", "endif", "ifdef", "ifndef"] preprocess :: [Token] -> (StateT PP IO) [Token] preprocess tokens = pp tokens >>= return . combineNumbers