From 7bc81ef67bdc138a5e57977553e2bb5500fa3c5b Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Thu, 28 Feb 2019 13:52:31 -0500 Subject: [PATCH] directory re-org; streamline build setup --- Makefile | 2 +- Args.hs => src/Args.hs | 0 Convert.hs => src/Convert.hs | 0 {Convert => src/Convert}/AlwaysKW.hs | 0 {Convert => src/Convert}/CaseKW.hs | 0 {Convert => src/Convert}/Logic.hs | 0 {Convert => src/Convert}/PackedArray.hs | 0 {Convert => src/Convert}/SplitPortDecl.hs | 0 {Convert => src/Convert}/StarPort.hs | 0 {Convert => src/Convert}/Traverse.hs | 0 {Convert => src/Convert}/Typedef.hs | 0 {Language => src/Language}/SystemVerilog.hs | 0 .../Language}/SystemVerilog/AST.hs | 0 .../Language}/SystemVerilog/Parser.hs | 0 .../Language}/SystemVerilog/Parser/Lex.x | 0 .../Language}/SystemVerilog/Parser/Parse.y | 0 .../SystemVerilog/Parser/Preprocess.hs | 0 .../Language}/SystemVerilog/Parser/Tokens.hs | 0 sv2v.hs => src/sv2v.hs | 0 sv2v.cabal | 48 +++++-------------- 20 files changed, 14 insertions(+), 36 deletions(-) rename Args.hs => src/Args.hs (100%) rename Convert.hs => src/Convert.hs (100%) rename {Convert => src/Convert}/AlwaysKW.hs (100%) rename {Convert => src/Convert}/CaseKW.hs (100%) rename {Convert => src/Convert}/Logic.hs (100%) rename {Convert => src/Convert}/PackedArray.hs (100%) rename {Convert => src/Convert}/SplitPortDecl.hs (100%) rename {Convert => src/Convert}/StarPort.hs (100%) rename {Convert => src/Convert}/Traverse.hs (100%) rename {Convert => src/Convert}/Typedef.hs (100%) rename {Language => src/Language}/SystemVerilog.hs (100%) rename {Language => src/Language}/SystemVerilog/AST.hs (100%) rename {Language => src/Language}/SystemVerilog/Parser.hs (100%) rename {Language => src/Language}/SystemVerilog/Parser/Lex.x (100%) rename {Language => src/Language}/SystemVerilog/Parser/Parse.y (100%) rename {Language => src/Language}/SystemVerilog/Parser/Preprocess.hs (100%) rename {Language => src/Language}/SystemVerilog/Parser/Tokens.hs (100%) rename sv2v.hs => src/sv2v.hs (100%) diff --git a/Makefile b/Makefile index ef22df2..429e9da 100644 --- a/Makefile +++ b/Makefile @@ -4,7 +4,7 @@ all: sv2v sv2v: mkdir -p bin - stack install --allow-different-user --install-ghc --local-bin-path bin + stack install --install-ghc --local-bin-path bin clean: stack clean diff --git a/Args.hs b/src/Args.hs similarity index 100% rename from Args.hs rename to src/Args.hs diff --git a/Convert.hs b/src/Convert.hs similarity index 100% rename from Convert.hs rename to src/Convert.hs diff --git a/Convert/AlwaysKW.hs b/src/Convert/AlwaysKW.hs similarity index 100% rename from Convert/AlwaysKW.hs rename to src/Convert/AlwaysKW.hs diff --git a/Convert/CaseKW.hs b/src/Convert/CaseKW.hs similarity index 100% rename from Convert/CaseKW.hs rename to src/Convert/CaseKW.hs diff --git a/Convert/Logic.hs b/src/Convert/Logic.hs similarity index 100% rename from Convert/Logic.hs rename to src/Convert/Logic.hs diff --git a/Convert/PackedArray.hs b/src/Convert/PackedArray.hs similarity index 100% rename from Convert/PackedArray.hs rename to src/Convert/PackedArray.hs diff --git a/Convert/SplitPortDecl.hs b/src/Convert/SplitPortDecl.hs similarity index 100% rename from Convert/SplitPortDecl.hs rename to src/Convert/SplitPortDecl.hs diff --git a/Convert/StarPort.hs b/src/Convert/StarPort.hs similarity index 100% rename from Convert/StarPort.hs rename to src/Convert/StarPort.hs diff --git a/Convert/Traverse.hs b/src/Convert/Traverse.hs similarity index 100% rename from Convert/Traverse.hs rename to src/Convert/Traverse.hs diff --git a/Convert/Typedef.hs b/src/Convert/Typedef.hs similarity index 100% rename from Convert/Typedef.hs rename to src/Convert/Typedef.hs diff --git a/Language/SystemVerilog.hs b/src/Language/SystemVerilog.hs similarity index 100% rename from Language/SystemVerilog.hs rename to src/Language/SystemVerilog.hs diff --git a/Language/SystemVerilog/AST.hs b/src/Language/SystemVerilog/AST.hs similarity index 100% rename from Language/SystemVerilog/AST.hs rename to src/Language/SystemVerilog/AST.hs diff --git a/Language/SystemVerilog/Parser.hs b/src/Language/SystemVerilog/Parser.hs similarity index 100% rename from Language/SystemVerilog/Parser.hs rename to src/Language/SystemVerilog/Parser.hs diff --git a/Language/SystemVerilog/Parser/Lex.x b/src/Language/SystemVerilog/Parser/Lex.x similarity index 100% rename from Language/SystemVerilog/Parser/Lex.x rename to src/Language/SystemVerilog/Parser/Lex.x diff --git a/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y similarity index 100% rename from Language/SystemVerilog/Parser/Parse.y rename to src/Language/SystemVerilog/Parser/Parse.y diff --git a/Language/SystemVerilog/Parser/Preprocess.hs b/src/Language/SystemVerilog/Parser/Preprocess.hs similarity index 100% rename from Language/SystemVerilog/Parser/Preprocess.hs rename to src/Language/SystemVerilog/Parser/Preprocess.hs diff --git a/Language/SystemVerilog/Parser/Tokens.hs b/src/Language/SystemVerilog/Parser/Tokens.hs similarity index 100% rename from Language/SystemVerilog/Parser/Tokens.hs rename to src/Language/SystemVerilog/Parser/Tokens.hs diff --git a/sv2v.hs b/src/sv2v.hs similarity index 100% rename from sv2v.hs rename to src/sv2v.hs diff --git a/sv2v.cabal b/sv2v.cabal index 8d335a3..ad091e3 100644 --- a/sv2v.cabal +++ b/sv2v.cabal @@ -1,49 +1,24 @@ -name: sv2v +name: sv2v version: 0.0.1 - -category: Language, Hardware, Embedded - synopsis: SystemVerilog to Verilog conversion - description: - A tool for coverting SystemVerilog to Verilog. Also exposes a limited - SystemVerilog parser and AST. Forked from the Verilog parser found at - https://github.com/tomahawkins/verilog + A tool for coverting SystemVerilog to Verilog. Originally forked from the + Verilog parser found at https://github.com/tomahawkins/verilog +category: Language, Hardware, Embedded, Development -author: Zachary Snow , Tom Hawkins +author: Zachary Snow , Tom Hawkins maintainer: Zachary Snow - -license: BSD3 +license: BSD3 license-file: LICENSE - homepage: https://github.com/zachjs/sv2v -build-type: Simple -cabal-version: >= 1.10 - -library - default-language: Haskell2010 - build-tools: - alex >= 3 && < 4, - happy >= 1 && < 2 - build-depends: - base >= 4.8.2.0 && < 5.0, - array >= 0.5.1.0 && < 0.6 - - exposed-modules: - Language.SystemVerilog - Language.SystemVerilog.AST - Language.SystemVerilog.Parser - Language.SystemVerilog.Parser.Lex - Language.SystemVerilog.Parser.Parse - Language.SystemVerilog.Parser.Preprocess - Language.SystemVerilog.Parser.Tokens - - ghc-options: -W +build-type: Simple +cabal-version: >= 1.12 executable sv2v default-language: Haskell2010 main-is: sv2v.hs + hs-source-dirs: src build-tools: alex >= 3 && < 4, happy >= 1 && < 2 @@ -54,7 +29,7 @@ executable sv2v containers, mtl other-modules: - Args + -- SystemVerilog modules Language.SystemVerilog Language.SystemVerilog.AST Language.SystemVerilog.Parser @@ -62,6 +37,7 @@ executable sv2v Language.SystemVerilog.Parser.Parse Language.SystemVerilog.Parser.Preprocess Language.SystemVerilog.Parser.Tokens + -- Conversion modules Convert Convert.AlwaysKW Convert.CaseKW @@ -71,6 +47,8 @@ executable sv2v Convert.StarPort Convert.Typedef Convert.Traverse + -- sv2v CLI modules + Args ghc-options: -O3 -threaded