diff --git a/src/Language/SystemVerilog/Parser/Lex.x b/src/Language/SystemVerilog/Parser/Lex.x
index 23edf98..a45bb7d 100644
--- a/src/Language/SystemVerilog/Parser/Lex.x
+++ b/src/Language/SystemVerilog/Parser/Lex.x
@@ -2,6 +2,7 @@
 {- sv2v
  - Author: Zachary Snow <zach@zachjs.com>
  - Original Lexer Author: Tom Hawkins <tomahawkins@gmail.com>
+ - vim: filetype=haskell
  -
  - SystemVerilog Lexer
  -
diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index c29de5a..ef27fab 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -1,6 +1,7 @@
 {- sv2v
  - Author: Zachary Snow <zach@zachjs.com>
  - Original Parser Author: Tom Hawkins <tomahawkins@gmail.com>
+ - vim: filetype=haskell
  -
  - This file has been *heavily* modified and extended from the original version
  - in tomahawkins/verilog. I have added support for numerous SystemVerilog