diff --git a/src/Convert/SystemTasks.hs b/src/Convert/SystemTasks.hs
index db881a0..269d3c9 100644
--- a/src/Convert/SystemTasks.hs
+++ b/src/Convert/SystemTasks.hs
@@ -10,9 +10,43 @@ import Convert.Traverse
 import Language.SystemVerilog.AST
 
 convert :: [AST] -> [AST]
-convert =
-    map $ traverseDescriptions $ traverseModuleItems $
-    traverseStmts $ traverseNestedStmts convertStmt
+convert = map $ traverseDescriptions $ traverseModuleItems convertModuleItem
+
+convertModuleItem :: ModuleItem -> ModuleItem
+
+convertModuleItem (ElabTask SeverityInfo args) =
+    Initial (Block Seq "" [] [
+        (Subroutine (Ident "$write") (Args [(String "Elaboration Info: ")] [])),
+        (Subroutine (Ident "$display") args)
+    ])
+
+convertModuleItem (ElabTask SeverityWarning args) =
+    Initial (Block Seq "" [] [
+        (Subroutine (Ident "$write") (Args [(String "Elaboration Warning: ")] [])),
+        (Subroutine (Ident "$display") args)
+    ])
+
+convertModuleItem (ElabTask SeverityError args) =
+    Initial (Block Seq "" [] [
+        (Subroutine (Ident "$write") (Args [(String "Elaboration Error: ")] [])),
+        (Subroutine (Ident "$display") args)
+    ])
+
+convertModuleItem (ElabTask SeverityFatal (Args [] [])) =
+    Initial (Block Seq "" [] [
+        (Subroutine (Ident "$display") (Args [(String "Elaboration Fatal:")] [])),
+        (Subroutine (Ident "$finish") (Args [] []))
+    ])
+
+convertModuleItem (ElabTask SeverityFatal (Args (finishArgs:displayArgs) _)) =
+    Initial (Block Seq "" [] [
+        (Subroutine (Ident "$write") (Args [(String "Elaboration Fatal: ")] [])),
+        (Subroutine (Ident "$display") (Args displayArgs [])),
+        (Subroutine (Ident "$finish") (Args [finishArgs] []))
+    ])
+
+convertModuleItem other =
+    traverseStmts (traverseNestedStmts convertStmt) other
 
 timeCall :: Expr
 timeCall = Call (Ident "$time") (Args [] [])
diff --git a/test/nosim/elab_task.sv b/test/core/elab_task.sv
similarity index 77%
rename from test/nosim/elab_task.sv
rename to test/core/elab_task.sv
index 87e14bb..03470af 100644
--- a/test/nosim/elab_task.sv
+++ b/test/core/elab_task.sv
@@ -6,5 +6,6 @@ module top;
     $error;
     $error("%b", 3);
     $fatal;
-    $fatal("%b", 4);
+    $fatal(0);
+    $fatal(0, "%b", 4);
 endmodule
diff --git a/test/core/elab_task.v b/test/core/elab_task.v
new file mode 100644
index 0000000..82223cc
--- /dev/null
+++ b/test/core/elab_task.v
@@ -0,0 +1,40 @@
+module top;
+	initial begin
+		$write("Elaboration Info: ");
+		$display;
+	end
+	initial begin
+		$write("Elaboration Info: ");
+		$display("%b", 1);
+	end
+	initial begin
+		$write("Elaboration Warning: ");
+		$display;
+	end
+	initial begin
+		$write("Elaboration Warning: ");
+		$display("%b", 2);
+	end
+	initial begin
+		$write("Elaboration Error: ");
+		$display;
+	end
+	initial begin
+		$write("Elaboration Error: ");
+		$display("%b", 3);
+	end
+	initial begin
+		$display("Elaboration Fatal:");
+		$finish;
+	end
+	initial begin
+		$write("Elaboration Fatal: ");
+		$display;
+		$finish(0);
+	end
+	initial begin
+		$write("Elaboration Fatal: ");
+		$display("%b", 4);
+		$finish(0);
+	end
+endmodule