From 7267f94b0b7ffda9be17f6477392996d246f2acc Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Mon, 16 Sep 2019 19:50:30 -0400 Subject: [PATCH] allow signing on net types (closes #40) --- src/Convert/DimensionQuery.hs | 2 +- src/Convert/Logic.hs | 4 ++-- src/Convert/ParamType.hs | 2 +- src/Convert/Traverse.hs | 2 +- src/Convert/Typedef.hs | 4 ++-- src/Language/SystemVerilog/AST/Type.hs | 6 +++--- src/Language/SystemVerilog/Parser/Parse.y | 2 +- 7 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/Convert/DimensionQuery.hs b/src/Convert/DimensionQuery.hs index 7beabf6..cf595d0 100644 --- a/src/Convert/DimensionQuery.hs +++ b/src/Convert/DimensionQuery.hs @@ -147,7 +147,7 @@ convertBits _ (Left t) = case elaborateType t of IntegerVector _ _ rs -> dimensionsSize rs Implicit _ rs -> dimensionsSize rs - Net _ rs -> dimensionsSize rs + Net _ _ rs -> dimensionsSize rs _ -> DimsFn FnBits $ Left t convertBits info (Right e) = case e of diff --git a/src/Convert/Logic.hs b/src/Convert/Logic.hs index 92e21af..31de09b 100644 --- a/src/Convert/Logic.hs +++ b/src/Convert/Logic.hs @@ -101,7 +101,7 @@ convertDescription ports orig = collectNestedExprsM exprIdents expr tmp = "sv2v_tmp_" ++ instanceName ++ "_" ++ portName tmpExpr = Ident tmp - t = Net TWire [(DimsFn FnBits $ Right expr, Number "1")] + t = Net TWire Unspecified [(DimsFn FnBits $ Right expr, Number "1")] items = [ MIPackageItem $ Decl $ Variable Local t tmp [] Nothing , AlwaysC AlwaysComb $ AsgnBlk AsgnOpEq lhs tmpExpr] @@ -118,7 +118,7 @@ convertDescription ports orig = where t = if sg /= Unspecified || Set.member ident idents then IntegerVector TReg sg - else Net TWire + else Net TWire sg convertModuleItem other = other -- all other logics (i.e. inside of functions) become regs convertDecl :: Decl -> Decl diff --git a/src/Convert/ParamType.hs b/src/Convert/ParamType.hs index 66f7dc0..5c97f74 100644 --- a/src/Convert/ParamType.hs +++ b/src/Convert/ParamType.hs @@ -218,7 +218,7 @@ isSimpleType :: Type -> Bool isSimpleType (IntegerVector _ _ _) = True isSimpleType (IntegerAtom _ _ ) = True isSimpleType (NonInteger _ ) = True -isSimpleType (Net _ _ ) = True +isSimpleType (Net _ _ _) = True isSimpleType _ = False -- attempt to rewrite instantiations with type parameters diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs index fdcb748..6616a2b 100644 --- a/src/Convert/Traverse.hs +++ b/src/Convert/Traverse.hs @@ -808,7 +808,7 @@ traverseNestedTypesM mapper = fullMapper where fullMapper t = tm t >>= mapper tm (Alias ps xx rs) = return $ Alias ps xx rs - tm (Net kw rs) = return $ Net kw rs + tm (Net kw sg rs) = return $ Net kw sg rs tm (Implicit sg rs) = return $ Implicit sg rs tm (IntegerVector kw sg rs) = return $ IntegerVector kw sg rs tm (IntegerAtom kw sg ) = return $ IntegerAtom kw sg diff --git a/src/Convert/Typedef.hs b/src/Convert/Typedef.hs index e638313..4b7533a 100644 --- a/src/Convert/Typedef.hs +++ b/src/Convert/Typedef.hs @@ -71,7 +71,7 @@ resolveItem :: Types -> (Type, Identifier) -> (Type, Identifier) resolveItem types (t, x) = (resolveType types t, x) resolveType :: Types -> Type -> Type -resolveType _ (Net kw rs) = Net kw rs +resolveType _ (Net kw sg rs) = Net kw sg rs resolveType _ (Implicit sg rs) = Implicit sg rs resolveType _ (IntegerVector kw sg rs) = IntegerVector kw sg rs resolveType _ (IntegerAtom kw sg ) = IntegerAtom kw sg @@ -86,7 +86,7 @@ resolveType types (Alias Nothing st rs1) = if Map.notMember st types then Alias Nothing st rs1 else case resolveType types $ types Map.! st of - (Net kw rs2) -> Net kw $ rs1 ++ rs2 + (Net kw sg rs2) -> Net kw sg $ rs1 ++ rs2 (Implicit sg rs2) -> Implicit sg $ rs1 ++ rs2 (IntegerVector kw sg rs2) -> IntegerVector kw sg $ rs1 ++ rs2 (Enum t v rs2) -> Enum t v $ rs1 ++ rs2 diff --git a/src/Language/SystemVerilog/AST/Type.hs b/src/Language/SystemVerilog/AST/Type.hs index 4c06328..57705eb 100644 --- a/src/Language/SystemVerilog/AST/Type.hs +++ b/src/Language/SystemVerilog/AST/Type.hs @@ -33,7 +33,7 @@ data Type = IntegerVector IntegerVectorType Signing [Range] | IntegerAtom IntegerAtomType Signing | NonInteger NonIntegerType - | Net NetType [Range] + | Net NetType Signing [Range] | Implicit Signing [Range] | Alias (Maybe Identifier) Identifier [Range] | Enum (Maybe Type) [Item] [Range] @@ -44,7 +44,7 @@ data Type instance Show Type where show (Alias ps xx rs) = printf "%s%s%s" (maybe "" (++ "::") ps) xx (showRanges rs) - show (Net kw rs) = printf "%s%s" (show kw) (showRanges rs) + show (Net kw sg rs) = printf "%s%s%s" (show kw) (showPadBefore sg) (showRanges rs) show (Implicit sg rs) = printf "%s%s" (showPad sg) (dropWhile (== ' ') $ showRanges rs) show (IntegerVector kw sg rs) = printf "%s%s%s" (show kw) (showPadBefore sg) (showRanges rs) show (IntegerAtom kw sg ) = printf "%s%s" (show kw) (showPadBefore sg) @@ -81,7 +81,7 @@ instance Ord (Signing -> [Range] -> Type) where typeRanges :: Type -> ([Range] -> Type, [Range]) typeRanges (Alias ps xx rs) = (Alias ps xx , rs) -typeRanges (Net kw rs) = (Net kw , rs) +typeRanges (Net kw sg rs) = (Net kw sg, rs) typeRanges (Implicit sg rs) = (Implicit sg, rs) typeRanges (IntegerVector kw sg rs) = (IntegerVector kw sg, rs) typeRanges (IntegerAtom kw sg ) = (nullRange $ IntegerAtom kw sg, []) diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index 0db397f..f20aba5 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -432,7 +432,7 @@ Type :: { Type } TypeNonIdent :: { Type } : PartialType OptSigning Dimensions { $1 $2 $3 } PartialType :: { Signing -> [Range] -> Type } - : NetType { \Unspecified -> Net $1 } + : NetType { Net $1 } | IntegerVectorType { IntegerVector $1 } | IntegerAtomType { \sg -> \[] -> IntegerAtom $1 sg } | NonIntegerType { \Unspecified -> \[] -> NonInteger $1 }