From 6cc4654ad6a87f2439432e5e7c0d4b4fc96c3eec Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Tue, 26 Mar 2019 15:21:06 -0400 Subject: [PATCH] support for real numbers --- src/Language/SystemVerilog/Parser/Lex.x | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/Language/SystemVerilog/Parser/Lex.x b/src/Language/SystemVerilog/Parser/Lex.x index 5b89945..8e2e3db 100644 --- a/src/Language/SystemVerilog/Parser/Lex.x +++ b/src/Language/SystemVerilog/Parser/Lex.x @@ -27,12 +27,17 @@ $decimalDigit = [0-9] @unsignedNumber = $decimalDigit ("_" | $decimalDigit)* +@sign = [\-\+] +@fixedPointNumber = @unsignedNumber "." @unsignedNumber +@floatingPointNumber = @unsignedNumber ("." @unsignedNumber)? [eE] @sign? @unsignedNumber + @size = @unsignedNumber " "? @decimalNumber = @size? @decimalBase " "? @unsignedNumber @binaryNumber = @size? @binaryBase " "? @binaryValue @octalNumber = @size? @octalBase " "? @octalValue @hexNumber = @size? @hexBase " "? @hexValue +@realNumber = @fixedPointNumber | @floatingPointNumber @unbasedUnsizedLiteral = "'" ( 0 | 1 | x | X | z | Z ) @@ -43,6 +48,7 @@ $decimalDigit = [0-9] | @binaryNumber | @hexNumber | @unbasedUnsizedLiteral + | @realNumber -- Strings