diff --git a/src/Language/SystemVerilog/AST/ModuleItem.hs b/src/Language/SystemVerilog/AST/ModuleItem.hs
index 7527cc8..7c6615b 100644
--- a/src/Language/SystemVerilog/AST/ModuleItem.hs
+++ b/src/Language/SystemVerilog/AST/ModuleItem.hs
@@ -119,15 +119,37 @@ data NInputGateKW
     | GateNor
     | GateXor
     | GateXnor
+    | GateBufif0
+    | GateBufif1
+    | GateNotif0
+    | GateNotif1
+    | GateCmos
+    | GateRcmos
+    | GateNmos
+    | GatePmos
+    | GateRnmos
+    | GateRpmos
     deriving Eq
 
 instance Show NInputGateKW where
-    show GateAnd  = "and"
-    show GateNand = "nand"
-    show GateOr   = "or"
-    show GateNor  = "nor"
-    show GateXor  = "xor"
-    show GateXnor = "xnor"
+    show GateAnd    = "and"
+    show GateNand   = "nand"
+    show GateOr     = "or"
+    show GateNor    = "nor"
+    show GateXor    = "xor"
+    show GateXnor   = "xnor"
+    show GateBufif0 = "bufif0"
+    show GateBufif1 = "bufif1"
+    show GateNotif0 = "notif0"
+    show GateNotif1 = "notif1"
+    -- these technically require exactly 3 inputs: input, ncontrol, pcontrol
+    show GateCmos   = "cmos"
+    show GateRcmos  = "rcmos"
+    -- these technically require exactly 2 inputs: input, enable
+    show GateNmos   = "nmos"
+    show GatePmos   = "pmos"
+    show GateRnmos  = "rnmos"
+    show GateRpmos  = "rpmos"
 
 data NOutputGateKW
     = GateBuf
diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 2fb2475..e09105a 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -872,12 +872,22 @@ OptGateName :: { (Identifier, [Range]) }
   | {- empty -} { ("", []) }
 
 NInputGateKW :: { NInputGateKW }
-  : "and"  { GateAnd  }
-  | "nand" { GateNand }
-  | "or"   { GateOr   }
-  | "nor"  { GateNor  }
-  | "xor"  { GateXor  }
-  | "xnor" { GateXnor }
+  : "and"    { GateAnd    }
+  | "nand"   { GateNand   }
+  | "or"     { GateOr     }
+  | "nor"    { GateNor    }
+  | "xor"    { GateXor    }
+  | "xnor"   { GateXnor   }
+  | "bufif0" { GateBufif0 }
+  | "bufif1" { GateBufif1 }
+  | "notif0" { GateNotif0 }
+  | "notif1" { GateNotif1 }
+  | "cmos"   { GateCmos   }
+  | "rcmos"  { GateRcmos  }
+  | "nmos"   { GateNmos   }
+  | "pmos"   { GatePmos   }
+  | "rnmos"  { GateRnmos  }
+  | "rpmos"  { GateRpmos  }
 NOutputGateKW :: { NOutputGateKW }
   : "buf"  { GateBuf  }
   | "not"  { GateNot  }
diff --git a/test/basic/gate.sv b/test/basic/gate.sv
index 93ae738..731595f 100644
--- a/test/basic/gate.sv
+++ b/test/basic/gate.sv
@@ -1,17 +1,31 @@
 module top;
-    reg input_a;
-    reg input_b;
-
-    wire output_and;
-    wire output_and_delay;
-    wire output_not;
-    wire output_buf_delay;
+    reg input_a, input_b, input_c;
 
+    wire output_and, output_and_delay;
+    wire output_not, output_buf_delay;
     and (output_and, input_a, input_b);
     and #1 (output_and_delay, input_a, input_b);
     not (output_not, input_a);
     buf #2 foo_name (output_buf_delay, input_a);
 
+    wire output_bufif0_delay, output_bufif1_delay;
+    wire output_notif0_delay, output_notif1_delay;
+    bufif0 (output_bufif0_delay, input_a, input_b);
+    bufif1 (output_bufif1_delay, input_a, input_b);
+    notif0 (output_notif0_delay, input_a, input_b);
+    notif1 (output_notif1_delay, input_a, input_b);
+
+    wire output_cmos, output_rcmos;
+    cmos (output_cmos, input_a, input_b, input_c);
+    rcmos (output_rcmos, input_a, input_b, input_c);
+
+    wire output_nmos, output_pmos;
+    wire output_rnmos, output_rpmos;
+    nmos (output_nmos, input_a, input_b);
+    pmos (output_pmos, input_a, input_b);
+    rnmos (output_rnmos, input_a, input_b);
+    rpmos (output_rpmos, input_a, input_b);
+
     wire output_nand, output_or, output_nor, output_xor, output_xnor;
     nand (output_nand, input_a, input_b);
     or (output_or, input_a, input_b);
@@ -24,20 +38,29 @@ module top;
             input_a, input_b,
             output_and, output_and_delay,
             output_not, output_buf_delay,
+            output_bufif0_delay, output_bufif1_delay,
+            output_notif0_delay, output_notif1_delay,
+            output_cmos, output_rcmos,
+            output_nmos, output_pmos,
+            output_rnmos, output_rpmos,
             output_nand, output_or, output_nor, output_xor, output_xnor);
 
         #1;
         #1; input_a = 1;
+        #1; input_c = 0;
         #1; input_b = 0;
         #1; input_b = 1;
+        #1; input_c = 1;
         #1;
 
         #1; input_a = 0;
         #1; input_b = 0;
         #1; input_a = 0;
         #1; input_b = 1;
+        #1; input_c = 0;
         #1; input_a = 1;
         #1; input_b = 0;
+        #1; input_c = 1;
         #1; input_a = 1;
         #1; input_b = 1;
         #1;