From 64f3067d78df52c9c12d234fa16bc3e81050aecc Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Wed, 17 Jun 2020 22:26:27 -0400 Subject: [PATCH] allow dimension shorthand for instance arrays --- src/Language/SystemVerilog/Parser/ParseDecl.hs | 2 ++ test/basic/instance_array.sv | 10 +++++----- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/Language/SystemVerilog/Parser/ParseDecl.hs b/src/Language/SystemVerilog/Parser/ParseDecl.hs index 36b2dc3..3b02c66 100644 --- a/src/Language/SystemVerilog/Parser/ParseDecl.hs +++ b/src/Language/SystemVerilog/Parser/ParseDecl.hs @@ -182,6 +182,7 @@ parseDTsAsIntantiations (DTIdent _ name : tokens) = follow = if null toks' then [] else step (tail toks') asRange :: DeclToken -> Range asRange (DTRange _ (NonIndexed, s)) = s + asRange (DTBit _ s) = (Number "0", BinOp Sub s (Number "1")) asRange _ = failure failure = error $ "unrecognized instantiation of " ++ name ++ ": " ++ show inst @@ -192,6 +193,7 @@ parseDTsAsIntantiations (DTIdent _ name : tokens) = isInstanceToken :: DeclToken -> Bool isInstanceToken (DTInstance{}) = True isInstanceToken (DTRange{}) = True + isInstanceToken (DTBit{}) = True isInstanceToken (DTIdent{}) = True isInstanceToken (DTComma{}) = True isInstanceToken _ = False diff --git a/test/basic/instance_array.sv b/test/basic/instance_array.sv index a8aea7e..2692416 100644 --- a/test/basic/instance_array.sv +++ b/test/basic/instance_array.sv @@ -4,11 +4,11 @@ module Example; endmodule module top; - Example e[2:0][4:5](); - defparam e[0][5].FOO = 1; - defparam e[0][4].FOO = 2; + Example e[3][4:5](); + defparam e[2][5].FOO = 1; + defparam e[2][4].FOO = 2; defparam e[1][5].FOO = 4; defparam e[1][4].FOO = 8; - defparam e[2][5].FOO = 16; - defparam e[2][4].FOO = 32; + defparam e[0][5].FOO = 16; + defparam e[0][4].FOO = 32; endmodule