From 5de77ab62d7d44299a7ca6353de5cf0605b4519e Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Tue, 26 Mar 2019 23:51:31 -0400 Subject: [PATCH] fix function and task input types --- src/Convert/Logic.hs | 13 ++++++++++--- src/Language/SystemVerilog/Parser/Parse.y | 8 ++++++-- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/src/Convert/Logic.hs b/src/Convert/Logic.hs index 0e81cf3..c0812b1 100644 --- a/src/Convert/Logic.hs +++ b/src/Convert/Logic.hs @@ -25,9 +25,17 @@ convert :: AST -> AST convert = traverseDescriptions convertDescription convertDescription :: Description -> Description -convertDescription (orig @ (Part _ Module _ _ _ _)) = - traverseModuleItems (traverseDecls convertDecl . convertModuleItem) orig +convertDescription orig = + if shouldConvert + then traverseModuleItems conversion orig + else orig where + shouldConvert = case orig of + Part _ Interface _ _ _ _ -> False + Part _ Module _ _ _ _ -> True + PackageItem _ -> True + Directive _ -> False + conversion = traverseDecls convertDecl . convertModuleItem idents = execWriter (collectModuleItemsM regIdents orig) convertModuleItem :: ModuleItem -> ModuleItem convertModuleItem (MIDecl (Variable dir (IntegerVector TLogic sg mr) ident a me)) = @@ -42,7 +50,6 @@ convertDescription (orig @ (Part _ Module _ _ _ _)) = convertDecl (Variable d (IntegerVector TLogic sg rs) x a me) = Variable d (IntegerVector TReg sg rs) x a me convertDecl other = other -convertDescription other = other regIdents :: ModuleItem -> Writer RegIdents () regIdents (AlwaysC _ stmt) = diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index 476f013..9045691 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -779,8 +779,12 @@ makeInput (Variable _ t x a me) = Variable Input t x a me makeInput other = error $ "unexpected non-var decl: " ++ (show other) defaultFuncInput :: Decl -> Decl -defaultFuncInput (Variable Input (Implicit sg rs) x a me) = - Variable Input (IntegerVector TLogic sg rs) x a me +defaultFuncInput (Variable dir (Implicit sg rs) x a me) = + Variable dir t x a me + where + t = if dir == Input || dir == Inout + then IntegerVector TLogic sg rs + else Implicit sg rs defaultFuncInput other = other combineTags :: Maybe Identifier -> Maybe Identifier -> Maybe Identifier