From 5b5bed8c7221369efd62ed68852e63f5fd389138 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 15 Feb 2022 15:38:16 +0100
Subject: [PATCH] fix dev iverilog test incompatibilities

---
 test/core/cast_top_item_tb.v    | 2 +-
 test/core/delay.sv              | 2 +-
 test/core/delay.v               | 2 +-
 test/core/interface_bundle.sv   | 2 +-
 test/core/interface_bundle.v    | 2 +-
 test/core/interface_generate.sv | 2 +-
 test/core/interface_generate.v  | 2 +-
 test/core/jump.sv               | 2 +-
 test/core/jump.v                | 2 +-
 9 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/test/core/cast_top_item_tb.v b/test/core/cast_top_item_tb.v
index a3647a6..062a411 100644
--- a/test/core/cast_top_item_tb.v
+++ b/test/core/cast_top_item_tb.v
@@ -1,7 +1,7 @@
 module top;
     genvar i;
     generate
-        for (i = 0; i < 32; i = i + 1)
+        for (i = 1; i < 32; i = i + 1)
             mod #(i) m();
     endgenerate
 endmodule
diff --git a/test/core/delay.sv b/test/core/delay.sv
index 742cb68..5b2c22c 100644
--- a/test/core/delay.sv
+++ b/test/core/delay.sv
@@ -9,6 +9,6 @@ module top;
         #1;
         #10; a = 'h5;
         #10;
-        $finish;
+        $finish(0);
     end
 endmodule
diff --git a/test/core/delay.v b/test/core/delay.v
index 396ceb1..531cbf6 100644
--- a/test/core/delay.v
+++ b/test/core/delay.v
@@ -9,6 +9,6 @@ module top;
         #1;
         #10; a = 'h5;
         #10;
-        $finish;
+        $finish(0);
     end
 endmodule
diff --git a/test/core/interface_bundle.sv b/test/core/interface_bundle.sv
index d0f4d2a..dc70f36 100644
--- a/test/core/interface_bundle.sv
+++ b/test/core/interface_bundle.sv
@@ -35,6 +35,6 @@ module top;
     initial begin
         $monitor("%b %b %b %b", b.index, b.clock, b.inp, b.out);
         #100;
-        $finish;
+        $finish(0);
     end
 endmodule
diff --git a/test/core/interface_bundle.v b/test/core/interface_bundle.v
index ba133cd..15f4297 100644
--- a/test/core/interface_bundle.v
+++ b/test/core/interface_bundle.v
@@ -23,7 +23,7 @@ module impl;
     initial begin
         $monitor("%b %b %b %b", b_index, b_clock, b_inp, b_out);
         #100;
-        $finish;
+        $finish(0);
     end
 endmodule
 
diff --git a/test/core/interface_generate.sv b/test/core/interface_generate.sv
index 238d134..9721311 100644
--- a/test/core/interface_generate.sv
+++ b/test/core/interface_generate.sv
@@ -48,6 +48,6 @@ module top;
 
     initial begin
         $monitor("%0d %b %b", $time, clock, intf.req);
-        #100 $finish;
+        #100 $finish(0);
     end
 endmodule
diff --git a/test/core/interface_generate.v b/test/core/interface_generate.v
index 770f2e6..bf935a6 100644
--- a/test/core/interface_generate.v
+++ b/test/core/interface_generate.v
@@ -52,6 +52,6 @@ module top;
 
     initial begin
         $monitor("%0d %b %b", $time, clock, intf.req);
-        #100 $finish;
+        #100 $finish(0);
     end
 endmodule
diff --git a/test/core/jump.sv b/test/core/jump.sv
index 3746bf8..73836e5 100644
--- a/test/core/jump.sv
+++ b/test/core/jump.sv
@@ -112,7 +112,7 @@ module top;
             break;
             $display("UNREACHABLE ", `__LINE__);
         end
-    initial #5 $finish;
+    initial #5 $finish(0);
 
     initial begin
         for (int unsigned i = 0; i < 5; ++i) begin
diff --git a/test/core/jump.v b/test/core/jump.v
index b162b32..0ca62f8 100644
--- a/test/core/jump.v
+++ b/test/core/jump.v
@@ -87,7 +87,7 @@ module top;
             i = 10;
         end
     end
-    initial #5 $finish;
+    initial #5 $finish(0);
 
     initial begin : loops_de
         reg unsigned [31:0] i;