From 527b59ff12d3272d7d5e0847cf1fc85d9445dfc1 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Wed, 4 Aug 2021 15:49:03 -0600 Subject: [PATCH] upgrade iverilog to lastest on v11-branch Workarounds for resolved iverilog issues have been removed. --- .github/workflows/main.yaml | 24 +++++++++++++----------- test/basic/multipack_prec.sv | 19 +++++++++++++++++++ test/basic/unnamed_genblk.sv | 25 ++++++++----------------- test/basic/unnamed_genblk_cascade.sv | 27 +++++++++------------------ test/core/multipack_prec.sv | 9 --------- test/core/multipack_prec.v | 11 ----------- test/core/multipack_prec.vh | 11 ----------- test/lib/functions.sh | 1 - 8 files changed, 49 insertions(+), 78 deletions(-) create mode 100644 test/basic/multipack_prec.sv delete mode 100644 test/core/multipack_prec.sv delete mode 100644 test/core/multipack_prec.v delete mode 100644 test/core/multipack_prec.vh diff --git a/.github/workflows/main.yaml b/.github/workflows/main.yaml index 7cc7b62..997ee13 100644 --- a/.github/workflows/main.yaml +++ b/.github/workflows/main.yaml @@ -40,31 +40,33 @@ jobs: - ubuntu-20.04 - macOS-10.15 needs: build + env: + IVERILOG_REF: 066eb0aca76f5bde06c63d67e605c07ef9f8be23 steps: - uses: actions/checkout@v1 - name: Install Dependencies (macOS) if: runner.os == 'macOS' - run: brew install shunit2 icarus-verilog + run: | + brew install shunit2 bison autoconf + echo "$(brew --prefix bison)/bin" >> $GITHUB_PATH - name: Install Dependencies (Linux) if: runner.os == 'Linux' run: sudo apt-get install -y shunit2 flex bison autoconf gperf - - name: Cache iverilog (Linux) + - name: Cache iverilog uses: actions/cache@v2 - if: runner.os == 'Linux' with: path: ~/.local - key: ${{ runner.OS }}-iverilog-11_0 - restore-keys: ${{ runner.OS }}-iverilog-11_0 - - name: Install iverilog (Linux) - if: runner.os == 'Linux' + key: ${{ runner.OS }}-${{ env.IVERILOG_REF }} + restore-keys: ${{ runner.OS }}-${{ env.IVERILOG_REF }} + - name: Install iverilog run: | if [ ! -e "$HOME/.local/bin/iverilog" ]; then - curl -L https://github.com/steveicarus/iverilog/archive/v11_0.tar.gz > iverilog.tar.gz - tar -xzf iverilog.tar.gz - cd iverilog-11_0 + git clone https://github.com/steveicarus/iverilog.git + cd iverilog + git checkout ${{ env.IVERILOG_REF }} autoconf ./configure --prefix=$HOME/.local - make + make -j2 make install cd .. fi diff --git a/test/basic/multipack_prec.sv b/test/basic/multipack_prec.sv new file mode 100644 index 0000000..5eb8504 --- /dev/null +++ b/test/basic/multipack_prec.sv @@ -0,0 +1,19 @@ +module top; + wire [3:0][2:0] arr1 [0:1]; + wire [0:1][3:0][2:0] arr2; + + assign arr1[0][0] = 3'b001; + assign arr1[0][1] = 3'b011; + assign arr1[0][2] = 3'b100; + assign arr1[0][3] = 3'b010; + assign arr1[1][0] = 3'b110; + assign arr1[1][1] = 3'b100; + assign arr1[1][2] = 3'b010; + assign arr1[1][3] = 3'b101; + + assign arr2[0][0] = arr1[0][0]; + assign arr2[0][1] = arr1[0][1]; + assign arr2[0][3:2] = arr1[0][3:2]; + assign arr2[1][0+:2] = arr1[1][0+:2]; + assign arr2[1][3-:2] = arr1[1][3-:2]; +endmodule diff --git a/test/basic/unnamed_genblk.sv b/test/basic/unnamed_genblk.sv index b5add5f..ea696a4 100644 --- a/test/basic/unnamed_genblk.sv +++ b/test/basic/unnamed_genblk.sv @@ -2,28 +2,20 @@ module mod; initial $dumpvars(0, mod); - // needed because of steveicarus/iverilog#528 - `ifdef __ICARUS__ - `define BEGIN(name) begin : name - `define END end - `else - `define BEGIN(name) - `define END - `endif parameter genblk2 = 0; genvar i; // The following generate block is implicitly named genblk1 - if (genblk2) `BEGIN(genblk1) logic a; `END // mod.genblk1.a - else `BEGIN(genblk1) logic b; `END // mod.genblk1.b + if (genblk2) logic a; // mod.genblk1.a + else logic b; // mod.genblk1.b // The following generate block is implicitly named genblk02 // as genblk2 is already a declared identifier - if (genblk2) `BEGIN(genblk02) logic a; `END // mod.genblk02.a - else `BEGIN(genblk02) logic b; `END // mod.genblk02.b + if (genblk2) logic a; // mod.genblk02.a + else logic b; // mod.genblk02.b // The following generate block would have been named genblk3 // but is explicitly named g1 @@ -31,7 +23,7 @@ module mod; for (i = 0; i < 1; i = i + 1) begin : g1 // block name // The following generate block is implicitly named genblk1 // as the first nested scope inside g1 - if (1) `BEGIN(genblk1) logic a; `END // mod.g1[0].genblk1.a + if (1) logic a; // mod.g1[0].genblk1.a end // The following generate block is implicitly named genblk4 since @@ -39,14 +31,13 @@ module mod; // The previous generate block would have been // named genblk3 if it had not been explicitly named g1 - for (i = 0; i < 1; i = i + 1) `BEGIN(genblk4) + for (i = 0; i < 1; i = i + 1) // The following generate block is implicitly named genblk1 // as the first nested generate block in genblk4 - if (1) `BEGIN(genblk1) logic a; `END // mod.genblk4[0].genblk1.a - `END + if (1) logic a; // mod.genblk4[0].genblk1.a // The following generate block is implicitly named genblk5 - if (1) `BEGIN(genblk5) logic a; `END // mod.genblk5.a + if (1) logic a; // mod.genblk5.a endmodule module top; diff --git a/test/basic/unnamed_genblk_cascade.sv b/test/basic/unnamed_genblk_cascade.sv index 67b178c..5bde7bf 100644 --- a/test/basic/unnamed_genblk_cascade.sv +++ b/test/basic/unnamed_genblk_cascade.sv @@ -1,33 +1,24 @@ module example; parameter P = 0; -// needed because of steveicarus/iverilog#528 -`ifdef __ICARUS__ - `define BEGIN begin : `BLK - `define END end -`else - `define BEGIN - `define END -`endif - `define BLK genblk1 - if (P == 1) `BEGIN integer w = 1; `END - else if (P == 2) `BEGIN integer x = 2; `END - else if (P == 3) `BEGIN integer y = 3; `END - else `BEGIN integer z = 9; `END + if (P == 1) integer w = 1; + else if (P == 2) integer x = 2; + else if (P == 3) integer y = 3; + else integer z = 9; `undef BLK `define BLK genblk2 case (P) - 1 : `BEGIN integer w = 1; `END - 2 : `BEGIN integer x = 2; `END - 3 : `BEGIN integer y = 3; `END - default: `BEGIN integer z = 9; `END + 1 : integer w = 1; + 2 : integer x = 2; + 3 : integer y = 3; + default: integer z = 9; endcase `undef BLK `define BLK genblk3 - if (1) `BEGIN wire a = 1; `END + if (1) wire a = 1; endmodule module top; diff --git a/test/core/multipack_prec.sv b/test/core/multipack_prec.sv deleted file mode 100644 index e9254ea..0000000 --- a/test/core/multipack_prec.sv +++ /dev/null @@ -1,9 +0,0 @@ -module top; - `include "multipack_prec.vh" - - assign arr2[0][0] = arr1[0][0]; - assign arr2[0][1] = arr1[0][1]; - assign arr2[0][3:2] = arr1[0][3:2]; - assign arr2[1][0+:2] = arr1[1][0+:2]; - assign arr2[1][3-:2] = arr1[1][3-:2]; -endmodule diff --git a/test/core/multipack_prec.v b/test/core/multipack_prec.v deleted file mode 100644 index 449e499..0000000 --- a/test/core/multipack_prec.v +++ /dev/null @@ -1,11 +0,0 @@ -module top; - `include "multipack_prec.vh" - - assign arr2[0][0] = arr1[0][0]; - assign arr2[0][1] = arr1[0][1]; - assign arr2[0][3:2] = arr1[0][3:2]; - // ideally we'd use the original as the reference, but the slices in the - // original fail due to steveicarus/iverilog#97 - assign arr2[1][1:0] = arr1[1][1:0]; - assign arr2[1][3:2] = arr1[1][3:2]; -endmodule diff --git a/test/core/multipack_prec.vh b/test/core/multipack_prec.vh deleted file mode 100644 index 84a7660..0000000 --- a/test/core/multipack_prec.vh +++ /dev/null @@ -1,11 +0,0 @@ -wire [3:0][2:0] arr1 [0:1]; -wire [0:1][3:0][2:0] arr2; - -assign arr1[0][0] = 3'b001; -assign arr1[0][1] = 3'b011; -assign arr1[0][2] = 3'b100; -assign arr1[0][3] = 3'b010; -assign arr1[1][0] = 3'b110; -assign arr1[1][1] = 3'b100; -assign arr1[1][2] = 3'b010; -assign arr1[1][3] = 3'b101; diff --git a/test/lib/functions.sh b/test/lib/functions.sh index 94dd1ac..0b4c9cd 100644 --- a/test/lib/functions.sh +++ b/test/lib/functions.sh @@ -21,7 +21,6 @@ simulate() { sim_prog=$SHUNIT_TMPDIR/simprog.exe iv_output=`iverilog \ -Wall \ - -Wno-select-range \ -Wno-portbind \ -o $sim_prog \ -g2005 \