From 519dbbeee13747f9224f698a103564ec1883a825 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Mon, 31 Jul 2023 23:00:47 -0400
Subject: [PATCH] restore distinction between generate and non-generate items

---
 src/Language/SystemVerilog/Parser/Parse.y | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 4226b38..0041a88 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -697,6 +697,8 @@ ModuleItems :: { [ModuleItem] }
 
 ModuleItem :: { [ModuleItem] }
   : NonGenerateModuleItem { $1 }
+  | ConditionalGenerateConstruct    { [Generate [$1]] }
+  | LoopGenerateConstruct           { [Generate [$1]] }
   | AttributeInstance ModuleItem    { map (addMIAttr $1) $2 }
   | "generate" GenItems endgenerate { [Generate $2] }
 NonGenerateModuleItemA :: { [ModuleItem] }
@@ -718,8 +720,6 @@ NonGenerateModuleItem :: { [ModuleItem] }
   | NInputGateKW  NInputGates  ";"       { map (\(a, b, c, d) -> NInputGate  $1 a b c d) $2 }
   | NOutputGateKW NOutputGates ";"       { map (\(a, b, c, d) -> NOutputGate $1 a b c d) $2 }
   | AssertionItem                        { [AssertionItem $1] }
-  | ConditionalGenerateConstruct         { [Generate [$1]] }
-  | LoopGenerateConstruct                { [Generate [$1]] }
 
 AssignOption :: { AssignOption }
   : {- empty -}   { AssignOptionNone }
@@ -1453,6 +1453,8 @@ GenItems :: { [GenItem] }
 GenItem :: { GenItem }
   : MITrace GenBlock              { uncurry GenBlock $2 }
   | MITrace NonGenerateModuleItemA { genItemsToGenItem $ map GenModuleItem $ addMITrace $1 $2 }
+  | MITrace ConditionalGenerateConstruct { $2 }
+  | MITrace LoopGenerateConstruct        { $2 }
 ConditionalGenerateConstruct :: { GenItem }
   : "if" "(" Expr ")" GenItemOrNull "else" GenItemOrNull { GenIf $3 $5 $7      }
   | "if" "(" Expr ")" GenItemOrNull %prec NoElse         { GenIf $3 $5 GenNull }