diff --git a/CHANGELOG.md b/CHANGELOG.md
index ae44b03..325d4a2 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -16,6 +16,8 @@
 * Fixed `logic` incorrectly converted to `wire` even when provided to a task or
   function output port
 * Fixed conversion of fields accessed from explicitly-cast structs
+* Fixed generated parameter name collisions when inlining interfaces and
+  interfaced-bound modules
 * Fixed conversion of enum item names and typenames nested deeply within the
   left-hand side of an assignment
 * Fixed `input signed` ports of interface-using modules producing invalid
diff --git a/src/Convert/Interface.hs b/src/Convert/Interface.hs
index 1ecdfb9..27c73d9 100644
--- a/src/Convert/Interface.hs
+++ b/src/Convert/Interface.hs
@@ -422,7 +422,7 @@ inlineInstance global ranges modportBindings items partName
         scoper = scopeModuleItem
             traverseDeclM traverseModuleItemM traverseGenItemM traverseStmtM
 
-        key = shortHash (partName, instanceName)
+        key = shortHash (partName, instanceName, hierarchyPath global)
 
         -- synthetic modports to be collected and removed after inlining
         bundleModport = Modport "" (impliedModport items)
diff --git a/test/core/interface_similar.sv b/test/core/interface_similar.sv
new file mode 100644
index 0000000..8de4071
--- /dev/null
+++ b/test/core/interface_similar.sv
@@ -0,0 +1,16 @@
+interface Interface;
+    parameter P;
+    logic [P - 1:0] x;
+endinterface
+module Module1(Interface i);
+    localparam P = i.P;
+    initial $display("Module1 P=%0d", P);
+endmodule
+module Module2(Interface i);
+    Interface #(i.P) i();
+    Module1 m(i);
+endmodule
+module top;
+    Interface #(5) i();
+    Module2 m(i);
+endmodule
diff --git a/test/core/interface_similar.v b/test/core/interface_similar.v
new file mode 100644
index 0000000..37e47d8
--- /dev/null
+++ b/test/core/interface_similar.v
@@ -0,0 +1,3 @@
+module top;
+    initial $display("Module1 P=%0d", 5);
+endmodule