diff --git a/src/Language/SystemVerilog/AST/Type.hs b/src/Language/SystemVerilog/AST/Type.hs
index a62e7f9..adefdd0 100644
--- a/src/Language/SystemVerilog/AST/Type.hs
+++ b/src/Language/SystemVerilog/AST/Type.hs
@@ -57,6 +57,7 @@ instance Show Type where
     show (Alias         xx    rs) = printf "%s%s" xx (showRanges rs)
     show (PSAlias ps    xx    rs) = printf "%s::%s%s" ps xx (showRanges rs)
     show (CSAlias ps pm xx    rs) = printf "%s#%s::%s%s" ps (showParams pm) xx (showRanges rs)
+    show (Implicit         sg []) = show sg
     show (Implicit         sg rs) = printf "%s%s"             (showPad       sg) (dropWhile (== ' ') $ showRanges rs)
     show (IntegerVector kw sg rs) = printf "%s%s%s" (show kw) (showPadBefore sg) (showRanges rs)
     show (IntegerAtom   kw sg   ) = printf "%s%s"   (show kw) (showPadBefore sg)
diff --git a/test/core/interface_input_type.sv.pat b/test/core/interface_input_type.sv.pat
new file mode 100644
index 0000000..02425e8
--- /dev/null
+++ b/test/core/interface_input_type.sv.pat
@@ -0,0 +1,2 @@
+reject wire signed  x;
+affirm wire signed x;
diff --git a/test/core/param_typeof.sv.pat b/test/core/param_typeof.sv.pat
new file mode 100644
index 0000000..7b23a31
--- /dev/null
+++ b/test/core/param_typeof.sv.pat
@@ -0,0 +1,2 @@
+reject parameter signed[15:0] X = 0;
+affirm parameter signed [15:0] X = 0;
diff --git a/test/core/unbased_unsized.sv.pat b/test/core/unbased_unsized.sv.pat
index 97e3eba..623b272 100644
--- a/test/core/unbased_unsized.sv.pat
+++ b/test/core/unbased_unsized.sv.pat
@@ -1 +1,3 @@
 affirm ? (* foo *) (* bar *)
+reject input wire  [W + 1:1] b;
+affirm input wire [W + 1:1] b;