From 4afd4f64b94e5dee64149d5741b3f0ae388d1280 Mon Sep 17 00:00:00 2001 From: Akihiko Odaki Date: Mon, 1 Sep 2025 20:06:55 +0900 Subject: [PATCH] add rpmos --- src/Language/SystemVerilog/AST/ModuleItem.hs | 2 ++ src/Language/SystemVerilog/Parser/Parse.y | 1 + test/basic/gate.sv | 2 ++ 3 files changed, 5 insertions(+) diff --git a/src/Language/SystemVerilog/AST/ModuleItem.hs b/src/Language/SystemVerilog/AST/ModuleItem.hs index 2daf568..d1a6fdf 100644 --- a/src/Language/SystemVerilog/AST/ModuleItem.hs +++ b/src/Language/SystemVerilog/AST/ModuleItem.hs @@ -118,6 +118,7 @@ data NInputGateKW | GateNand | GateOr | GateNor + | GateRpmos | GateXor | GateXnor deriving Eq @@ -128,6 +129,7 @@ instance Show NInputGateKW where show GateNand = "nand" show GateOr = "or" show GateNor = "nor" + show GateRpmos = "rpmos" show GateXor = "xor" show GateXnor = "xnor" diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index d0e46af..637dda3 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -877,6 +877,7 @@ NInputGateKW :: { NInputGateKW } | "nand" { GateNand } | "or" { GateOr } | "nor" { GateNor } + | "rpmos" { GateRpmos } | "xor" { GateXor } | "xnor" { GateXnor } NOutputGateKW :: { NOutputGateKW } diff --git a/test/basic/gate.sv b/test/basic/gate.sv index 2232ad5..de9652d 100644 --- a/test/basic/gate.sv +++ b/test/basic/gate.sv @@ -7,12 +7,14 @@ module top; wire output_not; wire output_buf_delay; wire output_bufif0_delay; + wire output_rpmos; and (output_and, input_a, input_b); and #1 (output_and_delay, input_a, input_b); not (output_not, input_a); buf #2 foo_name (output_buf_delay, input_a); bufif0 (output_bufif0_delay, input_a, input_b); + rpmos (output_rpmos, input_a, input_b); wire output_nand, output_or, output_nor, output_xor, output_xnor; nand (output_nand, input_a, input_b);