diff --git a/src/Convert/AlwaysKW.hs b/src/Convert/AlwaysKW.hs
index 1a57450..e0aeeaa 100644
--- a/src/Convert/AlwaysKW.hs
+++ b/src/Convert/AlwaysKW.hs
@@ -1,8 +1,9 @@
 {- sv2v
  - Author: Zachary Snow <zach@zachjs.com>
  -
- - Conversion for `always_comb` and `always_ff`
+ - Conversion for `always_latch`, `always_comb`, and `always_ff`
  -
+ - `always_latch` -> `always @*`
  - `always_comb` -> `always @*`
  - `always_ff` -> `always`
  -}
@@ -16,6 +17,8 @@ convert :: [AST] -> [AST]
 convert = map $ traverseDescriptions $ traverseModuleItems replaceAlwaysKW
 
 replaceAlwaysKW :: ModuleItem -> ModuleItem
+replaceAlwaysKW (AlwaysC AlwaysLatch stmt) =
+    AlwaysC Always $ Timing (Event SenseStar) stmt
 replaceAlwaysKW (AlwaysC AlwaysComb stmt) =
     AlwaysC Always $ Timing (Event SenseStar) stmt
 replaceAlwaysKW (AlwaysC AlwaysFF stmt) =
diff --git a/test/basic/always_latch.sv b/test/basic/always_latch.sv
new file mode 100644
index 0000000..1902317
--- /dev/null
+++ b/test/basic/always_latch.sv
@@ -0,0 +1,10 @@
+module test(a, b, en);
+    output logic a;
+    input logic b;
+    input logic en;
+    always_latch begin
+        if (en) begin
+            a <= b;
+        end
+    end
+endmodule
diff --git a/test/basic/always_latch.v b/test/basic/always_latch.v
new file mode 100644
index 0000000..65af123
--- /dev/null
+++ b/test/basic/always_latch.v
@@ -0,0 +1,10 @@
+module test(a, b, en);
+    output reg a;
+    input wire b;
+    input wire en;
+    always @(*) begin
+        if (en) begin
+            a <= b;
+        end
+    end
+endmodule
diff --git a/test/basic/always_latch_tb.v b/test/basic/always_latch_tb.v
new file mode 100644
index 0000000..df8d97f
--- /dev/null
+++ b/test/basic/always_latch_tb.v
@@ -0,0 +1,22 @@
+module top;
+    wire a;
+    reg b;
+    reg en;
+
+    initial begin
+        en = 1;
+        forever #1 en = ~en;
+    end
+
+    test m(.a, .b, .en);
+
+    initial begin
+        $monitor($time, a, b, en);
+        #1; b = 1;
+        #1; b = 0;
+        #1; b = 0;
+        #1; b = 1;
+        #1; b = 0;
+        $finish;
+    end
+endmodule