From 46242aac5dca6606d3e9f98a95dd9cced8f414bb Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Wed, 11 Sep 2019 18:54:51 +0200
Subject: [PATCH] fix combined array declarations (resolves #34)

---
 .../SystemVerilog/Parser/ParseDecl.hs         |  4 ++++
 test/basic/multi_array_decl.sv                | 19 +++++++++++++++++++
 test/basic/multi_array_decl.v                 | 11 +++++++++++
 3 files changed, 34 insertions(+)
 create mode 100644 test/basic/multi_array_decl.sv
 create mode 100644 test/basic/multi_array_decl.v

diff --git a/src/Language/SystemVerilog/Parser/ParseDecl.hs b/src/Language/SystemVerilog/Parser/ParseDecl.hs
index 5e77af7..930f29c 100644
--- a/src/Language/SystemVerilog/Parser/ParseDecl.hs
+++ b/src/Language/SystemVerilog/Parser/ParseDecl.hs
@@ -314,6 +314,10 @@ tripLookahead l0 =
     -- know we must have a valid triplet ahead
     else if null l1 || asgn /= Nothing then
         True
+    -- if there is an ident followed by some number of ranges, and that's it,
+    -- then there is a trailing declaration of an array ahead
+    else if (not $ null l1) && (null l2) then
+        True
     -- if there is a comma after the identifier (and optional ranges and
     -- assignment) that we're looking at, then we know this identifier is not a
     -- type name, as type names must be followed by a first identifier before a
diff --git a/test/basic/multi_array_decl.sv b/test/basic/multi_array_decl.sv
new file mode 100644
index 0000000..ce7113e
--- /dev/null
+++ b/test/basic/multi_array_decl.sv
@@ -0,0 +1,19 @@
+module top;
+    typedef struct packed {
+        logic f1;
+        logic f2;
+    } T;
+
+    T a[1:0];
+    T b[1:0];
+
+    T c[1:0], d[1:0];
+    T e[1:0], f[1:0], g;
+    T h, i[1:0];
+    T j;
+
+    struct packed {
+        logic f1;
+        logic f2;
+    } k;
+endmodule
diff --git a/test/basic/multi_array_decl.v b/test/basic/multi_array_decl.v
new file mode 100644
index 0000000..f32cfe7
--- /dev/null
+++ b/test/basic/multi_array_decl.v
@@ -0,0 +1,11 @@
+module top;
+    reg [1:0] a[1:0];
+    reg [1:0] b[1:0];
+
+    reg [1:0] c[1:0], d[1:0];
+    reg [1:0] e[1:0], f[1:0], g;
+    reg [1:0] h, i[1:0];
+    reg [1:0] j;
+
+    reg [1:0] k;
+endmodule