diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs
index f7d4e76..0cdf5fe 100644
--- a/src/Language/SystemVerilog/AST/Expr.hs
+++ b/src/Language/SystemVerilog/AST/Expr.hs
@@ -24,7 +24,7 @@ module Language.SystemVerilog.AST.Expr
     , pattern Mux
     ) where
 
-import Data.List (intercalate)
+import Data.List (intercalate, isPrefixOf)
 import Text.Printf (printf)
 
 import Language.SystemVerilog.AST.Number (Number(..))
@@ -138,8 +138,8 @@ instance Show Expr where
         showString " : " .
         shows f .
         showChar ')'
-    showsPrec _ (Call     e (Args [] [])) =
-        shows e
+    showsPrec _ (Call (Ident e) (Args [] [])) | "$" `isPrefixOf` e =
+        shows (Ident e)
     showsPrec _ (Call     e l  ) =
         shows e .
         shows l
diff --git a/test/nosim/system_tasks.sv b/test/core/system_tasks.sv
similarity index 100%
rename from test/nosim/system_tasks.sv
rename to test/core/system_tasks.sv
diff --git a/test/core/system_tasks.v b/test/core/system_tasks.v
new file mode 100644
index 0000000..362de49
--- /dev/null
+++ b/test/core/system_tasks.v
@@ -0,0 +1,22 @@
+module top;
+	initial begin
+		$write("[%0t] Info: ", $time);
+		$display;
+		$write("[%0t] Info: ", $time);
+		$display("%b", 1);
+		$write("[%0t] Warning: ", $time);
+		$display;
+		$write("[%0t] Warning: ", $time);
+		$display("%b", 2);
+		$write("[%0t] Error: ", $time);
+		$display;
+		$write("[%0t] Error: ", $time);
+		$display("%b", 3);
+		$write("[%0t] Fatal: ", $time);
+		$display;
+		$finish;
+		$write("Fatal:");
+		$display("%b", 4);
+		$finish(0);
+	end
+endmodule
diff --git a/test/lib/functions.sh b/test/lib/functions.sh
index 58570c1..8cf4db6 100644
--- a/test/lib/functions.sh
+++ b/test/lib/functions.sh
@@ -173,6 +173,11 @@ simulateAndCompare() {
     simulate $cvs_vcd $cvs_log $cs $tb
     simulate $cvv_vcd $cvv_log $cv $tb
 
+    # clean log files by removing filenames
+    sed -E 's#'$ve':[[:digit:]]+#'$ve'#g' $ref_log > $ref_log.tmp && mv $ref_log.tmp $ref_log
+    sed -E 's#'$cs':[[:digit:]]+#'$ve'#g' $cvs_log > $cvs_log.tmp && mv $cvs_log.tmp $cvs_log
+    sed -E 's#'$cv':[[:digit:]]+#'$ve'#g' $cvv_log > $cvv_log.tmp && mv $cvv_log.tmp $cvv_log
+
     # compare reference verilog to converted succinct
     output=`diff $ref_vcd $cvs_vcd`
     assertTrue "VE/CS VCDs are different:\n$output" $?