From 3db72c4c2df64f8d121229f1752604612bbc49f1 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 15 Feb 2022 17:49:50 +0100
Subject: [PATCH] logic conversion ignores LHSs in procedural assignment senses

---
 CHANGELOG.md                  |  2 ++
 src/Convert/Logic.hs          |  3 +++
 test/core/asgn_sense_lhs.sv   |  9 +++++++++
 test/core/asgn_sense_lhs.v    | 10 ++++++++++
 test/core/asgn_sense_lhs_tb.v | 10 ++++++++++
 5 files changed, 34 insertions(+)
 create mode 100644 test/core/asgn_sense_lhs.sv
 create mode 100644 test/core/asgn_sense_lhs.v
 create mode 100644 test/core/asgn_sense_lhs_tb.v

diff --git a/CHANGELOG.md b/CHANGELOG.md
index a663d82..4caf7d3 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -17,6 +17,8 @@
 
 * Fixed inadvertent design behavior changes caused by constant folding removing
   intentional width-extending operations such as `+ 0` and `* 1`
+* Fixed forced conversion to `reg` of data sensed in an edge-controlled
+  procedural assignment
 
 ## v0.0.9
 
diff --git a/src/Convert/Logic.hs b/src/Convert/Logic.hs
index 38dd211..085348c 100644
--- a/src/Convert/Logic.hs
+++ b/src/Convert/Logic.hs
@@ -186,6 +186,9 @@ traverseStmtM :: Stmt -> ST Stmt
 traverseStmtM stmt@Timing{} =
     -- ignore the timing LHSs
     return stmt
+traverseStmtM (Asgn op Just{} lhs expr) =
+    -- ignore the timing LHSs
+    traverseStmtM $ Asgn op Nothing lhs expr
 traverseStmtM stmt@(Subroutine (Ident f) (Args (_ : Ident x : _) [])) =
     when (f == "$readmemh" || f == "$readmemb") (collectLHSM $ LHSIdent x)
         >> return stmt
diff --git a/test/core/asgn_sense_lhs.sv b/test/core/asgn_sense_lhs.sv
new file mode 100644
index 0000000..a7848d9
--- /dev/null
+++ b/test/core/asgn_sense_lhs.sv
@@ -0,0 +1,9 @@
+module mod(input clk);
+    logic x, y, z;
+    initial begin
+        $display(x, y, z);
+        z = 1;
+        x = @(posedge y or posedge clk) z;
+        $display(x, y, z);
+    end
+endmodule
diff --git a/test/core/asgn_sense_lhs.v b/test/core/asgn_sense_lhs.v
new file mode 100644
index 0000000..e395848
--- /dev/null
+++ b/test/core/asgn_sense_lhs.v
@@ -0,0 +1,10 @@
+module mod(input clk);
+    reg x, z;
+    wire y;
+    initial begin
+        $display(x, y, z);
+        z = 1;
+        x = @(posedge y or posedge clk) z;
+        $display(x, y, z);
+    end
+endmodule
diff --git a/test/core/asgn_sense_lhs_tb.v b/test/core/asgn_sense_lhs_tb.v
new file mode 100644
index 0000000..25c3166
--- /dev/null
+++ b/test/core/asgn_sense_lhs_tb.v
@@ -0,0 +1,10 @@
+module top;
+    reg clk;
+    mod m(clk);
+    initial begin
+        $dumpvars(0, m);
+        clk = 0;
+        repeat (10)
+            #5 clk = ~clk;
+    end
+endmodule