From 3186afe400167deda60d36d23b4990a63a29cf6d Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Sat, 6 Jun 2020 23:17:13 -0400 Subject: [PATCH] additional expression simplification cases --- src/Language/SystemVerilog/AST/Expr.hs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs index 66a93dd..4422334 100644 --- a/src/Language/SystemVerilog/AST/Expr.hs +++ b/src/Language/SystemVerilog/AST/Expr.hs @@ -234,6 +234,12 @@ simplify (BinOp Sub (Number n1) (BinOp Sub (Number n2) e)) = simplify $ BinOp Add (BinOp Sub (Number n1) (Number n2)) e simplify (BinOp Sub (Number n1) (BinOp Sub e (Number n2))) = simplify $ BinOp Sub (BinOp Add (Number n1) (Number n2)) e +simplify (BinOp Sub (BinOp Add e (Number n1)) (Number n2)) = + simplify $ BinOp Add e (BinOp Sub (Number n1) (Number n2)) +simplify (BinOp Add (Number n1) (BinOp Add (Number n2) e)) = + simplify $ BinOp Add (BinOp Add (Number n1) (Number n2)) e +simplify (BinOp Ge (BinOp Sub e (Number "1")) (Number "0")) = + simplify $ BinOp Ge e (Number "1") simplify (BinOp Add (BinOp Sub (Number n1) e) (Number n2)) = case (readNumber n1, readNumber n2) of (Just x, Just y) ->