diff --git a/src/Convert/Unique.hs b/src/Convert/Unique.hs index a3990e7..e621835 100644 --- a/src/Convert/Unique.hs +++ b/src/Convert/Unique.hs @@ -3,9 +3,8 @@ - - Conversion for `unique`, `unique0`, and `priority` (verification checks) - - - This conversion simply drops these keywords, as they are only used for - - optimization and verification. There may be ways to communicate these - - attributes to certain downstream toolchains. + - This conversion adds full_case and parallel_case synthesis attributes + - for priority and unique respectively. -} module Convert.Unique (convert) where @@ -21,23 +20,16 @@ convert = convertStmt :: Stmt -> Stmt convertStmt (If _ cc s1 s2) = If NoCheck cc s1 s2 - convertStmt (Case Priority kw expr cases) = StmtAttr caseAttr caseStmt where caseAttr = Attr [("synthesis", Nil), ("full_case", Nil)] caseStmt = Case NoCheck kw expr cases - convertStmt (Case Unique kw expr cases) = StmtAttr caseAttr caseStmt where caseAttr = Attr [("synthesis", Nil), ("parallel_case", Nil)] caseStmt = Case NoCheck kw expr cases - convertStmt (Case Unique0 kw expr cases) = convertStmt (Case Unique kw expr cases) - -convertStmt (Case _ kw expr cases) = - Case NoCheck kw expr cases - convertStmt other = other diff --git a/test/core/case_violation_checks.sv b/test/core/case_violation_checks.sv index b26d5d4..5d2824f 100644 --- a/test/core/case_violation_checks.sv +++ b/test/core/case_violation_checks.sv @@ -1,20 +1,16 @@ - module top; - logic [1:0] select; - logic [2:0][3:0] data; - + reg [1:0] select; + logic [3:0] data [2:0]; UniqueCase case0(.select, .data(data[0])); Unique0Case case1(.select, .data(data[1])); PriorityCase case2(.select, .data(data[2])); - - initial ; + initial begin end endmodule module UniqueCase( input logic [1:0] select, output logic [3:0] data ); - always_comb begin data = 4'b0; unique case(select) @@ -23,14 +19,12 @@ module UniqueCase( 2'd2: data = 4'h3; endcase end - endmodule module Unique0Case( input logic [1:0] select, output logic [3:0] data ); - always_comb begin data = 4'b0; unique0 case(select) @@ -39,14 +33,12 @@ module Unique0Case( 2'd2: data = 4'h3; endcase end - endmodule module PriorityCase( input logic [1:0] select, output logic [3:0] data ); - always_comb begin data = 4'b0; priority case(select) @@ -55,5 +47,4 @@ module PriorityCase( 2'd2: data = 4'h3; endcase end - endmodule diff --git a/test/core/case_violation_checks.sv.pat b/test/core/case_violation_checks.sv.pat new file mode 100644 index 0000000..30facab --- /dev/null +++ b/test/core/case_violation_checks.sv.pat @@ -0,0 +1,2 @@ +affirm (* synthesis, parallel_case *) +affirm (* synthesis, full_case *) diff --git a/test/core/case_violation_checks.v b/test/core/case_violation_checks.v index c4e3c3c..67587c1 100644 --- a/test/core/case_violation_checks.v +++ b/test/core/case_violation_checks.v @@ -1,76 +1,50 @@ module top; - wire [1:0] select; - wire [11:0] data; - UniqueCase case0( - .select(select), - .data(data[0+:4]) - ); - Unique0Case case1( - .select(select), - .data(data[4+:4]) - ); - PriorityCase case2( - .select(select), - .data(data[8+:4]) - ); + reg [1:0] select; + wire [3:0] data [2:0]; + UniqueCase case0(.select(select), .data(data[0])); + Unique0Case case1(.select(select), .data(data[1])); + PriorityCase case2(.select(select), .data(data[2])); + initial begin end endmodule -module UniqueCase ( - select, - data + +module UniqueCase( + input [1:0] select, + output reg [3:0] data ); - reg _sv2v_0; - input wire [1:0] select; - output reg [3:0] data; - always @(*) begin - if (_sv2v_0) - ; - data = 4'b0000; - (* synthesis, parallel_case *) - case (select) - 2'd0: data = 4'ha; - 2'd1: data = 4'h6; - 2'd2: data = 4'h3; - endcase - end - initial _sv2v_0 = 0; + always @* begin + data = 4'b0; + case(select) + 2'd0: data = 4'ha; + 2'd1: data = 4'h6; + 2'd2: data = 4'h3; + endcase + end endmodule -module Unique0Case ( - select, - data + +module Unique0Case( + input [1:0] select, + output reg [3:0] data ); - reg _sv2v_0; - input wire [1:0] select; - output reg [3:0] data; - always @(*) begin - if (_sv2v_0) - ; - data = 4'b0000; - (* synthesis, parallel_case *) - case (select) - 2'd0: data = 4'ha; - 2'd1: data = 4'h6; - 2'd2: data = 4'h3; - endcase - end - initial _sv2v_0 = 0; + always @* begin + data = 4'b0; + case(select) + 2'd0: data = 4'ha; + 2'd1: data = 4'h6; + 2'd2: data = 4'h3; + endcase + end endmodule -module PriorityCase ( - select, - data + +module PriorityCase( + input [1:0] select, + output reg [3:0] data ); - reg _sv2v_0; - input wire [1:0] select; - output reg [3:0] data; - always @(*) begin - if (_sv2v_0) - ; - data = 4'b0000; - (* synthesis, full_case *) - case (select) - 2'd0: data = 4'ha; - 2'd1: data = 4'h6; - 2'd2: data = 4'h3; - endcase - end - initial _sv2v_0 = 0; + always @* begin + data = 4'b0; + case(select) + 2'd0: data = 4'ha; + 2'd1: data = 4'h6; + 2'd2: data = 4'h3; + endcase + end endmodule diff --git a/test/relong/case.v b/test/relong/case.v index b89681d..b369952 100644 --- a/test/relong/case.v +++ b/test/relong/case.v @@ -23,7 +23,6 @@ module UniqueCase( always @* begin data = 4'b0; // Unique keyword doesn't exist in Verilog - (* synthesis, parallel_case *) case(select) 2'd0: data = 4'ha; 2'd1: data = 4'h6; @@ -42,7 +41,6 @@ module WildcardCase( data = 4'b0; // Unique keyword doesn't exist in Verilog // casez doesn't exist in VTR, so manually elaborating it - (* synthesis, parallel_case *) case(select) // casez 2'b00: data = 4'h3; // 2'b1?: data = 4'hd; diff --git a/test/relong/fsm.v b/test/relong/fsm.v index ef998a5..620851c 100644 --- a/test/relong/fsm.v +++ b/test/relong/fsm.v @@ -18,7 +18,6 @@ module FSM( always @* begin nextState = currentState; - (* synthesis, parallel_case *) case(currentState) S_A: nextState = a ? S_B : S_C; S_B: nextState = a ? S_A : S_B; @@ -28,7 +27,6 @@ module FSM( always @* begin x = 1'b0; - (* synthesis, parallel_case *) case(currentState) S_A: x = ~a; S_B: x = 1'b1; @@ -36,4 +34,4 @@ module FSM( endcase end -endmodule +endmodule \ No newline at end of file diff --git a/test/relong/functions.v b/test/relong/functions.v index 3d0a348..a839346 100644 --- a/test/relong/functions.v +++ b/test/relong/functions.v @@ -24,7 +24,6 @@ module Example( // you expect a C function to do. Sadly VTR doesn't support the automatic // keyword. function [31:0] swapState(input [31:0] state); - (* synthesis, parallel_case *) case(state) // To return from a function assign the function name with a variable FOO: swapState = BAR; @@ -78,4 +77,4 @@ module Example( -endmodule +endmodule \ No newline at end of file