From 2f860ff220ec9e21a5a3d0b2f855a63eea43c80c Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Wed, 7 Jul 2021 20:14:11 -0400 Subject: [PATCH] fix trivial hash collisions Data.Hashable can produce hashes differing little in their upper bits if only the last character of the string is changed. Because we were using the upper bits of the hash in shortHash, this could lead to avoidable hash collisions. This change includes minor simplification optimizations which surfaced this collision in the existing struct_ident_scope test. --- src/Convert/ExprUtils.hs | 4 +++- src/Language/SystemVerilog/AST.hs | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/Convert/ExprUtils.hs b/src/Convert/ExprUtils.hs index 69c8c46..6679214 100644 --- a/src/Convert/ExprUtils.hs +++ b/src/Convert/ExprUtils.hs @@ -185,6 +185,7 @@ rangeSize (s, e) = -- returns the size of a range known to be ordered rangeSizeHiLo :: Range -> Expr +rangeSizeHiLo (SizedRange size) = size rangeSizeHiLo (hi, lo) = simplify $ BinOp Add (BinOp Sub hi lo) (RawNum 1) @@ -206,9 +207,10 @@ endianCondRange r r1 r2 = -- returns the total size of a set of dimensions dimensionsSize :: [Range] -> Expr +dimensionsSize [] = RawNum 1 dimensionsSize ranges = simplify $ - foldl (BinOp Mul) (RawNum 1) $ + foldl1 (BinOp Mul) $ map rangeSize $ ranges diff --git a/src/Language/SystemVerilog/AST.hs b/src/Language/SystemVerilog/AST.hs index 37cbfaa..ae9dbfd 100644 --- a/src/Language/SystemVerilog/AST.hs +++ b/src/Language/SystemVerilog/AST.hs @@ -32,6 +32,7 @@ module Language.SystemVerilog.AST ) where import Text.Printf (printf) +import Data.Bits ((.&.)) import Data.Hashable (hash) import Language.SystemVerilog.AST.Attr as Attr @@ -82,5 +83,5 @@ lhsToExpr (LHSStream o e ls) = Stream o e $ map lhsToExpr ls shortHash :: (Show a) => a -> String shortHash x = - take 5 $ printf "%05X" val + printf "%05X" $ val .&. 0xFFFFF where val = hash $ show x