From 2ee837f7b0358e5cd125545e3a1d454c6c199b81 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Tue, 9 Apr 2019 12:50:56 -0400
Subject: [PATCH] restore port-decl hoisting for cleaner output

---
 src/Convert.hs                |  2 ++
 src/Convert/HoistPortDecls.hs | 36 +++++++++++++++++++++++++++++++++++
 sv2v.cabal                    |  1 +
 3 files changed, 39 insertions(+)
 create mode 100644 src/Convert/HoistPortDecls.hs

diff --git a/src/Convert.hs b/src/Convert.hs
index a658313..4d3a6dc 100644
--- a/src/Convert.hs
+++ b/src/Convert.hs
@@ -26,6 +26,7 @@ import qualified Convert.Struct
 import qualified Convert.Typedef
 import qualified Convert.UnbasedUnsized
 import qualified Convert.Unique
+import qualified Convert.HoistPortDecls
 
 type Phase = AST -> AST
 
@@ -37,6 +38,7 @@ phases excludes =
     , selectExclude (Job.Logic    , Convert.Logic.convert)
     , Convert.FuncRet.convert
     , Convert.Enum.convert
+    , Convert.HoistPortDecls.convert
     , Convert.KWArgs.convert
     , Convert.PackedArray.convert
     , Convert.StarPort.convert
diff --git a/src/Convert/HoistPortDecls.hs b/src/Convert/HoistPortDecls.hs
new file mode 100644
index 0000000..2556ccb
--- /dev/null
+++ b/src/Convert/HoistPortDecls.hs
@@ -0,0 +1,36 @@
+{- sv2v
+ - Author: Zachary Snow <zach@zachjs.com>
+ -
+ - VCS doesn't like port declarations inside of `generate` blocks, so we hoist
+ - them out with this conversion. This obviously isn't ideal, but it's
+ - relatively straightforward, and testing in VCS is important.
+ -}
+
+module Convert.HoistPortDecls (convert) where
+
+import Data.List (partition)
+
+import Convert.Traverse
+import Language.SystemVerilog.AST
+
+convert :: AST -> AST
+convert = traverseDescriptions hoistPortDecls
+
+hoistPortDecls :: Description -> Description
+hoistPortDecls (Part extern kw lifetime name ports items) =
+    Part extern kw lifetime name ports (concat $ map explode items)
+    where
+        explode :: ModuleItem -> [ModuleItem]
+        explode (Generate genItems) =
+            if null rest
+                then portDecls
+                else portDecls ++ [Generate rest]
+            where
+                (wrappedPortDecls, rest) = partition isPortDecl genItems
+                portDecls = map (\(GenModuleItem item) -> item) wrappedPortDecls
+                isPortDecl :: GenItem -> Bool
+                isPortDecl (GenModuleItem (MIDecl (Variable dir _ _ _ _))) =
+                    dir /= Local
+                isPortDecl _ = False
+        explode other = [other]
+hoistPortDecls other = other
diff --git a/sv2v.cabal b/sv2v.cabal
index 12ecc93..45d82a4 100644
--- a/sv2v.cabal
+++ b/sv2v.cabal
@@ -58,6 +58,7 @@ executable sv2v
     Convert.Bits
     Convert.Enum
     Convert.FuncRet
+    Convert.HoistPortDecls
     Convert.Interface
     Convert.KWArgs
     Convert.Logic