From 2d8e6bddd318521d67fa29c68c4f20355d872db6 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Sun, 22 Sep 2019 23:29:02 -0400 Subject: [PATCH] parser rejects function input decls with bad directions --- src/Language/SystemVerilog/Parser/Parse.y | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index ea2dbc3..312e58e 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -1218,8 +1218,10 @@ combineDeclsAndStmts :: ([Decl], [Stmt]) -> ([Decl], [Stmt]) -> ([Decl], [Stmt]) combineDeclsAndStmts (a1, b1) (a2, b2) = (a1 ++ a2, b1 ++ b2) makeInput :: Decl -> Decl -makeInput (Variable _ t x a me) = Variable Input t x a me -makeInput other = error $ "unexpected non-var decl: " ++ (show other) +makeInput (Variable Local t x a me) = Variable Input t x a me +makeInput (Variable Input t x a me) = Variable Input t x a me +makeInput other = + error $ "unexpected non-var or non-input decl: " ++ (show other) defaultFuncInput :: Decl -> Decl defaultFuncInput (Variable dir (Implicit sg rs) x a me) =