diff --git a/src/Convert/SizeCast.hs b/src/Convert/SizeCast.hs index 2c46b98..e9ec593 100644 --- a/src/Convert/SizeCast.hs +++ b/src/Convert/SizeCast.hs @@ -66,8 +66,8 @@ traverseExprM = where str = (show size) ++ "'d" ++ (show num) size = s' - num = if size == 32 - then n' + num = if size >= 32 + then n' -- already read as 32 bits else n' `mod` (2 ^ s') _ -> convertCastM (Number s) (Number n) convertExprM (orig @ (Cast (Right DimsFn{}) _)) = diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs index 2031f8a..52f1603 100644 --- a/src/Language/SystemVerilog/AST/Expr.hs +++ b/src/Language/SystemVerilog/AST/Expr.hs @@ -207,7 +207,13 @@ readNumber ('\'' : 'h' : rest) = case readHex rest of [(v, _)] -> Just v _ -> Nothing -readNumber n = readMaybe n +readNumber n = + case readMaybe n of + Nothing -> Nothing + Just res -> + if show res == n + then Just res + else Nothing showUniOpPrec :: Expr -> ShowS showUniOpPrec (e @ UniOp{}) = (showParen True . shows) e diff --git a/test/basic/cast.sv b/test/basic/cast.sv index 51d755e..abef50e 100644 --- a/test/basic/cast.sv +++ b/test/basic/cast.sv @@ -23,6 +23,12 @@ module top; $display("%0d %0d", y, ($clog2(WIDTH))'(y)); $display("%0d %0d", z, ($clog2(WIDTH))'(z)); $display("%b", 32'(4)); + $display("%b", 33'(4)); + $display("%b", 33'(64'hFFFF_FFFF_FFFF_FFFF)); + $display("%b", 32'(4294967296)); + $display("%b", 33'(4294967296)); + $display("%b", 32'(4294967297)); + $display("%b", 33'(4294967297)); end localparam bit foo = '0; diff --git a/test/basic/cast.v b/test/basic/cast.v index 22ceaca..96c1cac 100644 --- a/test/basic/cast.v +++ b/test/basic/cast.v @@ -26,6 +26,12 @@ module top; $display("%0d %0d", y, $signed(y[4:0])); $display("%0d %0d", z, z[4:0]); $display("%b", 32'd4); + $display("%b", 33'd4); + $display("%b", 33'h1_FFFF_FFFF); + $display("%b", 32'd0); + $display("%b", 33'd4294967296); + $display("%b", 32'd1); + $display("%b", 33'd4294967297); end localparam [0:0] foo = 0;