From 1f7c70dfe11c501a0c39d2d060e04ccd63fbd142 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Mon, 2 Sep 2019 20:46:35 -0400 Subject: [PATCH] language support for LHS streaming operators --- src/Convert/AsgnOp.hs | 11 ++++++----- src/Convert/Struct.hs | 2 ++ src/Convert/Traverse.hs | 14 +++++++++----- src/Language/SystemVerilog/AST.hs | 3 +++ src/Language/SystemVerilog/AST/LHS.hs | 5 ++++- src/Language/SystemVerilog/Parser/Parse.y | 10 ++++++++-- src/Language/SystemVerilog/Parser/ParseDecl.hs | 7 +++++-- 7 files changed, 37 insertions(+), 15 deletions(-) diff --git a/src/Convert/AsgnOp.hs b/src/Convert/AsgnOp.hs index 8a808d0..2275d90 100644 --- a/src/Convert/AsgnOp.hs +++ b/src/Convert/AsgnOp.hs @@ -37,8 +37,9 @@ convertStmt (AsgnBlk (AsgnOp op) lhs expr) = convertStmt other = other lhsToExpr :: LHS -> Expr -lhsToExpr (LHSIdent x ) = Ident x -lhsToExpr (LHSBit l e ) = Bit (lhsToExpr l) e -lhsToExpr (LHSRange l m r) = Range (lhsToExpr l) m r -lhsToExpr (LHSDot l x ) = Dot (lhsToExpr l) x -lhsToExpr (LHSConcat ls ) = Concat $ map lhsToExpr ls +lhsToExpr (LHSIdent x ) = Ident x +lhsToExpr (LHSBit l e ) = Bit (lhsToExpr l) e +lhsToExpr (LHSRange l m r ) = Range (lhsToExpr l) m r +lhsToExpr (LHSDot l x ) = Dot (lhsToExpr l) x +lhsToExpr (LHSConcat ls) = Concat $ map lhsToExpr ls +lhsToExpr (LHSStream o e ls) = Stream o e $ map lhsToExpr ls diff --git a/src/Convert/Struct.hs b/src/Convert/Struct.hs index a1bc19f..a51cd49 100644 --- a/src/Convert/Struct.hs +++ b/src/Convert/Struct.hs @@ -288,6 +288,8 @@ convertAsgn structs types (lhs, expr) = fieldType = lookupFieldType fields x convertLHS (LHSConcat lhss) = (Implicit Unspecified [], LHSConcat $ map (snd . convertLHS) lhss) + convertLHS (LHSStream o e lhss) = + (Implicit Unspecified [], LHSStream o e $ map (snd . convertLHS) lhss) -- try expression conversion by looking at the *outermost* type first convertExpr :: Type -> Expr -> Expr diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs index 4bb867a..a6cdc55 100644 --- a/src/Convert/Traverse.hs +++ b/src/Convert/Traverse.hs @@ -504,6 +504,9 @@ exprMapperHelpers exprMapper = rangeMapper r >>= return . LHSRange l m lhsMapper (LHSBit l e) = exprMapper e >>= return . LHSBit l + lhsMapper (LHSStream o e ls) = do + e' <- exprMapper e + return $ LHSStream o e' ls lhsMapper other = return other traverseExprsM' :: Monad m => TFStrategy -> MapperM m Expr -> MapperM m ModuleItem @@ -730,11 +733,12 @@ traverseNestedLHSsM :: Monad m => MapperM m LHS -> MapperM m LHS traverseNestedLHSsM mapper = fullMapper where fullMapper lhs = mapper lhs >>= tl - tl (LHSIdent x ) = return $ LHSIdent x - tl (LHSBit l e ) = fullMapper l >>= \l' -> return $ LHSBit l' e - tl (LHSRange l m r) = fullMapper l >>= \l' -> return $ LHSRange l' m r - tl (LHSDot l x ) = fullMapper l >>= \l' -> return $ LHSDot l' x - tl (LHSConcat lhss ) = mapM fullMapper lhss >>= return . LHSConcat + tl (LHSIdent x ) = return $ LHSIdent x + tl (LHSBit l e ) = fullMapper l >>= \l' -> return $ LHSBit l' e + tl (LHSRange l m r ) = fullMapper l >>= \l' -> return $ LHSRange l' m r + tl (LHSDot l x ) = fullMapper l >>= \l' -> return $ LHSDot l' x + tl (LHSConcat lhss) = mapM fullMapper lhss >>= return . LHSConcat + tl (LHSStream o e lhss) = mapM fullMapper lhss >>= return . LHSStream o e traverseNestedLHSs :: Mapper LHS -> Mapper LHS traverseNestedLHSs = unmonad traverseNestedLHSsM diff --git a/src/Language/SystemVerilog/AST.hs b/src/Language/SystemVerilog/AST.hs index 7795c22..54a401c 100644 --- a/src/Language/SystemVerilog/AST.hs +++ b/src/Language/SystemVerilog/AST.hs @@ -55,4 +55,7 @@ exprToLHS (Dot l x ) = do exprToLHS (Concat ls ) = do ls' <- mapM exprToLHS ls Just $ LHSConcat ls' +exprToLHS (Stream o e ls) = do + ls' <- mapM exprToLHS ls + Just $ LHSStream o e ls' exprToLHS _ = Nothing diff --git a/src/Language/SystemVerilog/AST/LHS.hs b/src/Language/SystemVerilog/AST/LHS.hs index 7fde305..b2e4d64 100644 --- a/src/Language/SystemVerilog/AST/LHS.hs +++ b/src/Language/SystemVerilog/AST/LHS.hs @@ -14,6 +14,7 @@ import Text.Printf (printf) import Language.SystemVerilog.AST.ShowHelp (commas) import Language.SystemVerilog.AST.Type (Identifier) import Language.SystemVerilog.AST.Expr (Expr, PartSelectMode, Range) +import Language.SystemVerilog.AST.Op (StreamOp) data LHS = LHSIdent Identifier @@ -21,6 +22,7 @@ data LHS | LHSRange LHS PartSelectMode Range | LHSDot LHS Identifier | LHSConcat [LHS] + | LHSStream StreamOp Expr [LHS] deriving Eq instance Show LHS where @@ -28,4 +30,5 @@ instance Show LHS where show (LHSBit l e ) = printf "%s[%s]" (show l) (show e) show (LHSRange l m (a, b)) = printf "%s[%s%s%s]" (show l) (show a) (show m) (show b) show (LHSDot l x ) = printf "%s.%s" (show l) x - show (LHSConcat lhss ) = printf "{%s}" (commas $ map show lhss) + show (LHSConcat lhss) = printf "{%s}" (commas $ map show lhss) + show (LHSStream o e lhss) = printf "{%s %s%s}" (show o) (show e) (show $ LHSConcat lhss) diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index 4c96a3e..f02d8ca 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -423,12 +423,14 @@ DeclOrStmtToken :: { DeclToken } | Identifier { DTIdent $1 } | Direction { DTDir $1 } | "[" Expr "]" { DTBit $2 } - | "{" LHSs "}" { DTConcat $2 } + | LHSConcat { DTConcat $1 } | PartialType { DTType $1 } | "." Identifier { DTDot $2 } | Signing { DTSigning $1 } | Lifetime { DTLifetime $1 } | Identifier "::" Identifier { DTPSIdent $1 $3 } + | "{" StreamOp StreamSize Concat "}" { DTStream $2 $3 (map toLHS $4) } + | "{" StreamOp Concat "}" { DTStream $2 (Number "1") (map toLHS $3) } VariablePortIdentifiers :: { [(Identifier, Maybe Expr)] } : VariablePortIdentifier { [$1] } @@ -654,8 +656,12 @@ LHS :: { LHS } | LHS PartSelect { LHSRange $1 (fst $2) (snd $2) } | LHS "[" Expr "]" { LHSBit $1 $3 } | LHS "." Identifier { LHSDot $1 $3 } - | "{" LHSs "}" { LHSConcat $2 } + | LHSConcat { LHSConcat $1 } + | "{" StreamOp StreamSize Concat "}" { LHSStream $2 $3 (map toLHS $4) } + | "{" StreamOp Concat "}" { LHSStream $2 (Number "1") (map toLHS $3) } +LHSConcat :: { [LHS] } + : "{" LHSs "}" { $2 } LHSs :: { [LHS] } : LHS { [$1] } | LHSs "," LHS { $1 ++ [$3] } diff --git a/src/Language/SystemVerilog/Parser/ParseDecl.hs b/src/Language/SystemVerilog/Parser/ParseDecl.hs index 1e53aee..0cff5df 100644 --- a/src/Language/SystemVerilog/Parser/ParseDecl.hs +++ b/src/Language/SystemVerilog/Parser/ParseDecl.hs @@ -57,6 +57,7 @@ data DeclToken | DTInstance [PortBinding] | DTBit Expr | DTConcat [LHS] + | DTStream StreamOp Expr [LHS] | DTDot Identifier | DTSigning Signing | DTLifetime Lifetime @@ -229,6 +230,7 @@ parseDTsAsDeclsAndAsgns tokens = isAsgnToken :: DeclToken -> Bool isAsgnToken (DTBit _) = True isAsgnToken (DTConcat _) = True +isAsgnToken (DTStream _ _ _) = True isAsgnToken (DTDot _) = True isAsgnToken (DTAsgnNBlk _ _) = True isAsgnToken (DTAsgn (AsgnOp _) _) = True @@ -240,8 +242,9 @@ takeLHS (t : ts) = foldl takeLHSStep (takeLHSStart t) ts takeLHSStart :: DeclToken -> Maybe LHS -takeLHSStart (DTConcat lhss) = Just $ LHSConcat lhss -takeLHSStart (DTIdent x ) = Just $ LHSIdent x +takeLHSStart (DTConcat lhss) = Just $ LHSConcat lhss +takeLHSStart (DTStream o e lhss) = Just $ LHSStream o e lhss +takeLHSStart (DTIdent x ) = Just $ LHSIdent x takeLHSStart _ = Nothing takeLHSStep :: Maybe LHS -> DeclToken -> Maybe LHS