diff --git a/src/Convert/Logic.hs b/src/Convert/Logic.hs
index 02c6688..cc51c07 100644
--- a/src/Convert/Logic.hs
+++ b/src/Convert/Logic.hs
@@ -118,7 +118,7 @@ traverseModuleItem ports scopes =
                     ]
             where
                 t = Net (NetType TWire) Unspecified
-                        [(DimsFn FnBits $ Right expr, RawNum 1)]
+                        [(DimsFn FnBits $ Right $ lhsToExpr lhs, RawNum 1)]
                 x = "sv2v_tmp_" ++ shortHash (lhs, expr)
         -- rewrite port bindings to use temporary nets where necessary
         fixModuleItem (Instance moduleName params instanceName rs bindings) =
diff --git a/test/basic/logic_struct_select.sv b/test/basic/logic_struct_select.sv
new file mode 100644
index 0000000..34d0af2
--- /dev/null
+++ b/test/basic/logic_struct_select.sv
@@ -0,0 +1,22 @@
+module example(sel, out);
+    parameter W = 8;
+
+    typedef struct packed {
+        logic [W/2-1:0] x;
+        logic [W/2-1:0] y;
+    } line_t;
+
+    line_t [3:0] arr;
+    initial begin
+        arr[0] = 8'b01000011;
+        arr[1] = 8'b00010110;
+        arr[2] = 8'b10001111;
+        arr[3] = 8'b01100110;
+    end
+
+    input logic [1:0] sel;
+    output line_t out;
+
+    assign out.x = sel ? arr[sel].x : '0;
+    always @* out.y = sel ? arr[sel].y : '0;
+endmodule
diff --git a/test/basic/logic_struct_select.v b/test/basic/logic_struct_select.v
new file mode 100644
index 0000000..f1be83e
--- /dev/null
+++ b/test/basic/logic_struct_select.v
@@ -0,0 +1,16 @@
+module example(sel, out);
+    parameter W = 8;
+
+    reg [7:0] arr [3:0];
+    initial begin
+        arr[0] = 8'b01000011;
+        arr[1] = 8'b00010110;
+        arr[2] = 8'b10001111;
+        arr[3] = 8'b01100110;
+    end
+
+    input [1:0] sel;
+    output [7:0] out;
+
+    assign out = sel ? arr[sel] : 8'b0;
+endmodule
diff --git a/test/basic/logic_struct_select_tb.v b/test/basic/logic_struct_select_tb.v
new file mode 100644
index 0000000..d512c5d
--- /dev/null
+++ b/test/basic/logic_struct_select_tb.v
@@ -0,0 +1,9 @@
+module top;
+    reg [1:0] sel;
+    wire [7:0] out;
+    example e(.sel, .out);
+    integer i = 0;
+    initial
+        for (i = 0; i < 10; i = i + 1)
+            #1 sel = i;
+endmodule