diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index a1bdee0..7b1da8a 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -388,7 +388,7 @@ string             { Token Lit_string      _ _ }
 %left  "^" "^~" "~^"
 %left  "&" "~&"
 %left  "==" "!=" "===" "!==" "==?" "!=?"
-%left  "<" "<=" ">" ">="
+%left  "<" "<=" ">" ">=" "inside" "dist"
 %left  "<<" ">>" "<<<" ">>>"
 %left  "+" "-"
 %left  "*" "/" "%"
@@ -999,6 +999,7 @@ Expr :: { Expr }
   | "'" "{" PatternItems "}"    { Pattern $3 }
   | "{" StreamOp StreamSize Concat "}" { Stream $2 $3           $4 }
   | "{" StreamOp            Concat "}" { Stream $2 (Number "1") $3 }
+  | Expr "inside" Concat        { foldl1 (BinOp LogOr) $ map (BinOp Eq $1) $3 }
   -- binary expressions
   | Expr "||"  Expr { BinOp LogOr  $1 $3 }
   | Expr "&&"  Expr { BinOp LogAnd $1 $3 }
diff --git a/test/basic/inside_expr.sv b/test/basic/inside_expr.sv
new file mode 100644
index 0000000..7fd00f5
--- /dev/null
+++ b/test/basic/inside_expr.sv
@@ -0,0 +1,9 @@
+module top;
+    initial
+        for (logic [1:0] a = 0; a < 3; a++) begin
+            if (a inside {2'b01, 2'b00})
+                $display("fizz");
+            if (a inside {2'b10})
+                $display("buzz");
+        end
+endmodule
diff --git a/test/basic/inside_expr.v b/test/basic/inside_expr.v
new file mode 100644
index 0000000..61bd9c9
--- /dev/null
+++ b/test/basic/inside_expr.v
@@ -0,0 +1,11 @@
+module top;
+    initial begin : foo
+        reg [1:0] a;
+        for (a = 0; a < 3; a++) begin
+            if (a == 2'b01 || a == 2'b00)
+                $display("fizz");
+            if (a == 2'b10)
+                $display("buzz");
+        end
+    end
+endmodule