From 1a394cff9cca4cae431188d83aac486a43e1568b Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Sun, 6 Oct 2019 16:13:34 -0400 Subject: [PATCH] support mintypmax expressions --- src/Convert/Struct.hs | 6 ++++++ src/Convert/Traverse.hs | 5 +++++ src/Language/SystemVerilog/AST/Expr.hs | 2 ++ src/Language/SystemVerilog/Parser/Parse.y | 2 ++ 4 files changed, 15 insertions(+) diff --git a/src/Convert/Struct.hs b/src/Convert/Struct.hs index 1756358..0f2d957 100644 --- a/src/Convert/Struct.hs +++ b/src/Convert/Struct.hs @@ -475,6 +475,12 @@ convertAsgn structs types (lhs, expr) = where items' = map mapItem items mapItem (mx, e) = (mx, snd $ convertSubExpr e) + convertSubExpr (MinTypMax a b c) = + (t, MinTypMax a' b' c') + where + (_, a') = convertSubExpr a + (t, b') = convertSubExpr b + (_, c') = convertSubExpr c convertSubExpr Nil = (Implicit Unspecified [], Nil) convertTypeOrExpr :: TypeOrExpr -> TypeOrExpr diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs index 34f4a71..d46bd5e 100644 --- a/src/Convert/Traverse.hs +++ b/src/Convert/Traverse.hs @@ -481,6 +481,11 @@ traverseNestedExprsM mapper = exprMapper let names = map fst l exprs <- mapM exprMapper $ map snd l return $ Pattern $ zip names exprs + em (MinTypMax e1 e2 e3) = do + e1' <- exprMapper e1 + e2' <- exprMapper e2 + e3' <- exprMapper e3 + return $ MinTypMax e1' e2' e3' em (Nil) = return Nil exprMapperHelpers :: Monad m => MapperM m Expr -> diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs index a9ae5cc..9a0ef6b 100644 --- a/src/Language/SystemVerilog/AST/Expr.hs +++ b/src/Language/SystemVerilog/AST/Expr.hs @@ -55,6 +55,7 @@ data Expr | DimFn DimFn TypeOrExpr Expr | Dot Expr Identifier | Pattern [(Maybe Identifier, Expr)] + | MinTypMax Expr Expr Expr | Nil deriving (Eq, Ord) @@ -83,6 +84,7 @@ instance Show Expr where showPatternItem :: (Maybe Identifier, Expr) -> String showPatternItem (Nothing, e) = show e showPatternItem (Just n , e) = printf "%s: %s" n (show e) + show (MinTypMax a b c) = printf "(%s : %s : %s)" (show a) (show b) (show c) data Args = Args [Maybe Expr] [(Identifier, Maybe Expr)] diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y index ed15bb6..6df0e1a 100644 --- a/src/Language/SystemVerilog/Parser/Parse.y +++ b/src/Language/SystemVerilog/Parser/Parse.y @@ -1019,6 +1019,7 @@ DelayValue :: { Expr } : Number { Number $1 } | Identifier { Ident $1 } | Identifier "::" Identifier { PSIdent $1 $3 } + | "(" Expr ":" Expr ":" Expr ")" { MinTypMax $2 $4 $6 } -- TODO: Support these other DelayValues? -- | real_number -- | time_literal @@ -1106,6 +1107,7 @@ Expr :: { Expr } | "{" StreamOp StreamSize Concat "}" { Stream $2 $3 $4 } | "{" StreamOp Concat "}" { Stream $2 (Number "1") $3 } | Expr "inside" Concat { foldl1 (BinOp LogOr) $ map (BinOp Eq $1) $3 } + | "(" Expr ":" Expr ":" Expr ")" { MinTypMax $2 $4 $6 } -- binary expressions | Expr "||" Expr { BinOp LogOr $1 $3 } | Expr "&&" Expr { BinOp LogAnd $1 $3 }