From 190c2488ccb659ad54e3d17c1fb2d1bfdcb81fc5 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Wed, 7 Jul 2021 22:15:51 -0400
Subject: [PATCH] remove unused typeclass derivations

---
 src/Job.hs                                  | 6 +++---
 src/Language/SystemVerilog/AST/Op.hs        | 2 +-
 src/Language/SystemVerilog/AST/Type.hs      | 8 ++++----
 src/Language/SystemVerilog/Parser/Tokens.hs | 2 --
 4 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/src/Job.hs b/src/Job.hs
index 59a056d..d57636b 100644
--- a/src/Job.hs
+++ b/src/Job.hs
@@ -24,13 +24,13 @@ data Exclude
     | Interface
     | Logic
     | Succinct
-    deriving (Show, Typeable, Data, Eq)
+    deriving (Typeable, Data, Eq)
 
 data Write
     = Stdout
     | Adjacent
     | File FilePath
-    deriving (Show, Typeable, Data, Eq)
+    deriving (Typeable, Data)
 
 data Job = Job
     { files :: [FilePath]
@@ -43,7 +43,7 @@ data Job = Job
     , verbose :: Bool
     , write :: Write
     , writeRaw :: String
-    } deriving (Show, Typeable, Data)
+    } deriving (Typeable, Data)
 
 version :: String
 version =
diff --git a/src/Language/SystemVerilog/AST/Op.hs b/src/Language/SystemVerilog/AST/Op.hs
index 3812970..5c4c6ca 100644
--- a/src/Language/SystemVerilog/AST/Op.hs
+++ b/src/Language/SystemVerilog/AST/Op.hs
@@ -102,7 +102,7 @@ data AsgnOp
     = AsgnOpEq
     | AsgnOpNonBlocking
     | AsgnOp BinOp
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show AsgnOp where
     show AsgnOpEq = "="
diff --git a/src/Language/SystemVerilog/AST/Type.hs b/src/Language/SystemVerilog/AST/Type.hs
index d3355c1..1ee0572 100644
--- a/src/Language/SystemVerilog/AST/Type.hs
+++ b/src/Language/SystemVerilog/AST/Type.hs
@@ -226,7 +226,7 @@ data Strength
     = DefaultStrength
     | DriveStrength Strength0 Strength1
     | ChargeStrength ChargeStrength
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show Strength where
     show DefaultStrength = ""
@@ -239,7 +239,7 @@ data Strength0
     | Pull0
     | Weak0
     | Highz0
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show Strength0 where
     show Supply0 = "supply0"
@@ -254,7 +254,7 @@ data Strength1
     | Pull1
     | Weak1
     | Highz1
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show Strength1 where
     show Supply1 = "supply1"
@@ -267,7 +267,7 @@ data ChargeStrength
     = Small
     | Medium
     | Large
-    deriving (Eq, Ord)
+    deriving Eq
 
 instance Show ChargeStrength where
     show Small  = "small"
diff --git a/src/Language/SystemVerilog/Parser/Tokens.hs b/src/Language/SystemVerilog/Parser/Tokens.hs
index ebc6877..e86e439 100644
--- a/src/Language/SystemVerilog/Parser/Tokens.hs
+++ b/src/Language/SystemVerilog/Parser/Tokens.hs
@@ -32,14 +32,12 @@ pattern TokenEOF = Token Unknown "" (Position "" 0 0)
 
 data Position
     = Position String Int Int
-    deriving Eq
 
 instance Show Position where
     show (Position f l c) = printf "%s:%d:%d" f l c
 
 data Token
     = Token TokenName String Position
-    deriving (Show, Eq)
 
 data TokenName
     = KW_dollar_bits