From 14644cd1ed6ed1bc9900b6f28cbba5c9aef53701 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Sun, 9 Feb 2020 14:01:05 -0500
Subject: [PATCH] fix output of empty generate loops

---
 src/Language/SystemVerilog/AST/GenItem.hs | 2 +-
 test/basic/for_decl.sv                    | 1 +
 test/basic/for_decl.v                     | 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/Language/SystemVerilog/AST/GenItem.hs b/src/Language/SystemVerilog/AST/GenItem.hs
index 673a6a4..5c026fb 100644
--- a/src/Language/SystemVerilog/AST/GenItem.hs
+++ b/src/Language/SystemVerilog/AST/GenItem.hs
@@ -45,7 +45,7 @@ instance Show GenItem where
             x1 (show e1)
             (show c)
             x2 (show o2) (show e2)
-            (show s)
+            (if s == GenNull then "begin end" else show s)
     show (GenNull) = ";"
     show (GenModuleItem item) = show item
 
diff --git a/test/basic/for_decl.sv b/test/basic/for_decl.sv
index 3c6e8a6..98578d1 100644
--- a/test/basic/for_decl.sv
+++ b/test/basic/for_decl.sv
@@ -69,6 +69,7 @@ module top;
         ;
         for (genvar n = 0; n < 32; n = n + 1)
             assign c[n] = n & 1;
+        for (genvar m = 0; m < 32; m = m + 1) begin end
     endgenerate
 
 endmodule
diff --git a/test/basic/for_decl.v b/test/basic/for_decl.v
index d3c1ef0..8ddba7d 100644
--- a/test/basic/for_decl.v
+++ b/test/basic/for_decl.v
@@ -79,6 +79,7 @@ module top;
     generate
         for (n = 0; n < 32; n = n + 1)
             assign c[n] = n & 1;
+        for (n = 0; n < 32; n = n + 1) begin end
     endgenerate
 
 endmodule