From 08c38e619306b6445b7d4e0961ce4d64739998d9 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Sun, 6 Oct 2019 21:21:58 -0400
Subject: [PATCH] support time literals as expressions

---
 src/Convert/Struct.hs                     | 1 +
 src/Convert/Traverse.hs                   | 1 +
 src/Language/SystemVerilog/AST/Expr.hs    | 2 ++
 src/Language/SystemVerilog/Parser/Parse.y | 1 +
 4 files changed, 5 insertions(+)

diff --git a/src/Convert/Struct.hs b/src/Convert/Struct.hs
index 0f2d957..b1e071b 100644
--- a/src/Convert/Struct.hs
+++ b/src/Convert/Struct.hs
@@ -441,6 +441,7 @@ convertAsgn structs types (lhs, expr) =
             (Implicit Unspecified [], Call (Just x) f args)
         convertSubExpr (String s) = (Implicit Unspecified [], String s)
         convertSubExpr (Number n) = (Implicit Unspecified [], Number n)
+        convertSubExpr (Time   n) = (Implicit Unspecified [], Time   n)
         convertSubExpr (PSIdent x y) = (Implicit Unspecified [], PSIdent x y)
         convertSubExpr (Repeat e es) =
             (Implicit Unspecified [], Repeat e' es')
diff --git a/src/Convert/Traverse.hs b/src/Convert/Traverse.hs
index d46bd5e..26a3db8 100644
--- a/src/Convert/Traverse.hs
+++ b/src/Convert/Traverse.hs
@@ -426,6 +426,7 @@ traverseNestedExprsM mapper = exprMapper
             exprMapper e >>= return . Right
         em (String s) = return $ String s
         em (Number s) = return $ Number s
+        em (Time   s) = return $ Time   s
         em (Ident  i) = return $ Ident  i
         em (PSIdent x y) = return $ PSIdent x y
         em (Range e m (e1, e2)) = do
diff --git a/src/Language/SystemVerilog/AST/Expr.hs b/src/Language/SystemVerilog/AST/Expr.hs
index 9a0ef6b..0d068f0 100644
--- a/src/Language/SystemVerilog/AST/Expr.hs
+++ b/src/Language/SystemVerilog/AST/Expr.hs
@@ -39,6 +39,7 @@ type TypeOrExpr = Either Type Expr
 data Expr
     = String  String
     | Number  String
+    | Time    String
     | Ident   Identifier
     | PSIdent Identifier Identifier
     | Range   Expr PartSelectMode Range
@@ -62,6 +63,7 @@ data Expr
 instance Show Expr where
     show (Nil          ) = ""
     show (Number  str  ) = str
+    show (Time    str  ) = str
     show (Ident   str  ) = str
     show (PSIdent x y  ) = printf "%s::%s" x y
     show (String  str  ) = printf "\"%s\"" str
diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 6df0e1a..86b9f54 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -1085,6 +1085,7 @@ Expr :: { Expr }
   : "(" Expr ")"                { $2 }
   | String                      { String $1 }
   | Number                      { Number $1 }
+  | Time                        { Time   $1 }
   |                 Identifier CallArgs { Call (Nothing) $1 $2 }
   | Identifier "::" Identifier CallArgs { Call (Just $1) $3 $4 }
   | DimsFn "(" TypeOrExpr ")"   { DimsFn $1 $3 }