diff --git a/src/Language/SystemVerilog/AST/GenItem.hs b/src/Language/SystemVerilog/AST/GenItem.hs
index 930af6a..1f7d1a1 100644
--- a/src/Language/SystemVerilog/AST/GenItem.hs
+++ b/src/Language/SystemVerilog/AST/GenItem.hs
@@ -17,7 +17,7 @@ import Language.SystemVerilog.AST.ShowHelp
 import Language.SystemVerilog.AST.Expr (Expr)
 import Language.SystemVerilog.AST.Op (AsgnOp)
 import Language.SystemVerilog.AST.Type (Identifier)
-import {-# SOURCE #-} Language.SystemVerilog.AST.ModuleItem (ModuleItem)
+import {-# SOURCE #-} Language.SystemVerilog.AST.ModuleItem (ModuleItem, showGenModuleItem)
 
 data GenItem
     = GenBlock Identifier [GenItem]
@@ -36,21 +36,23 @@ instance Show GenItem where
         printf "case (%s)\n%s\nendcase" (show e) bodyStr
         where bodyStr = indent $ unlines' $ map showGenCase cs
     show (GenIf e a GenNull) = printf "if (%s) %s"          (show e) (showBareBlock a)
+    -- showBlockedBranch avoids dangling else ambiguity
     show (GenIf e a b      ) = printf "if (%s) %s\nelse %s" (show e) (showBlockedBranch a) (showBareBlock b)
     show (GenFor (x1, e1) c (x2, o2, e2) s) =
         printf "for (%s = %s; %s; %s %s %s) %s"
             x1 (show e1)
             (show c)
             x2 (show o2) (show e2)
-            (showBareBlock s)
-    show (GenNull) = ";"
-    show (GenModuleItem item) = show item
+            (showBlockedBranch s) -- Verilog 2001 requires this to be a block
+    show (GenNull) = ""
+    show (GenModuleItem item) = showGenModuleItem item
 
 showBareBlock :: GenItem -> String
 showBareBlock (GenBlock x i) =
     printf "begin%s\n%s\nend"
         (if null x then "" else " : " ++ x)
         (indent $ show i)
+showBareBlock (GenNull) = ";"
 showBareBlock item = show item
 
 showBlockedBranch :: GenItem -> String
diff --git a/src/Language/SystemVerilog/AST/ModuleItem.hs b/src/Language/SystemVerilog/AST/ModuleItem.hs
index fc19c47..e2324fa 100644
--- a/src/Language/SystemVerilog/AST/ModuleItem.hs
+++ b/src/Language/SystemVerilog/AST/ModuleItem.hs
@@ -14,6 +14,7 @@ module Language.SystemVerilog.AST.ModuleItem
     , NOutputGateKW (..)
     , AssignOption  (..)
     , AssertionItem (..)
+    , showGenModuleItem
     ) where
 
 import Data.List (intercalate)
@@ -94,6 +95,10 @@ showModportDecl (dir, ident, e) =
         then printf "%s %s" (show dir) ident
         else printf "%s .%s(%s)" (show dir) ident (show e)
 
+showGenModuleItem :: ModuleItem -> String
+showGenModuleItem (Generate genItems) = show genItems
+showGenModuleItem item = show item
+
 type PortBinding = (Identifier, Expr)
 
 type ModportDecl = (Direction, Identifier, Expr)
diff --git a/src/Language/SystemVerilog/AST/ModuleItem.hs-boot b/src/Language/SystemVerilog/AST/ModuleItem.hs-boot
index 9a3054b..1c17dfb 100644
--- a/src/Language/SystemVerilog/AST/ModuleItem.hs-boot
+++ b/src/Language/SystemVerilog/AST/ModuleItem.hs-boot
@@ -1,7 +1,10 @@
 module Language.SystemVerilog.AST.ModuleItem
     ( ModuleItem
+    , showGenModuleItem
     ) where
 
 data ModuleItem
 instance Eq ModuleItem
 instance Show ModuleItem
+
+showGenModuleItem :: ModuleItem -> String
diff --git a/src/Language/SystemVerilog/Parser/Parse.y b/src/Language/SystemVerilog/Parser/Parse.y
index 93f7fec..dab4880 100644
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@@ -705,7 +705,11 @@ ModuleItem :: { [ModuleItem] }
   : NonGenerateModuleItem { $1 }
   | ConditionalGenerateConstruct    { [Generate [$1]] }
   | LoopGenerateConstruct           { [Generate [$1]] }
+  | AttributeInstance ModuleItem    { map (addMIAttr $1) $2 }
   | "generate" GenItems endgenerate { [Generate $2] }
+NonGenerateModuleItemA :: { [ModuleItem] }
+  : NonGenerateModuleItem                    { $1 }
+  | AttributeInstance NonGenerateModuleItemA { map (addMIAttr $1) $2 }
 NonGenerateModuleItem :: { [ModuleItem] }
   -- This item covers module instantiations and all declarations
   : ModuleDeclTokens(";")                {% mapM recordPartUsed $ parseDTsAsModuleItems $1 }
@@ -721,7 +725,6 @@ NonGenerateModuleItem :: { [ModuleItem] }
   | TaskOrFunction                       { [MIPackageItem $1] }
   | NInputGateKW  NInputGates  ";"       { map (\(a, b, c, d) -> NInputGate  $1 a b c d) $2 }
   | NOutputGateKW NOutputGates ";"       { map (\(a, b, c, d) -> NOutputGate $1 a b c d) $2 }
-  | AttributeInstance ModuleItem         { map (addMIAttr $1) $2 }
   | AssertionItem                        { [AssertionItem $1] }
 
 AssignOption :: { AssignOption }
@@ -1469,8 +1472,7 @@ GenItems :: { [GenItem] }
 
 GenItem :: { GenItem }
   : MITrace GenBlock              { uncurry GenBlock $2 }
-  | MITrace NonGenerateModuleItem { genItemsToGenItem $ map GenModuleItem $ addMITrace $1 $2 }
-  | MITrace "generate" GenItems "endgenerate" { genItemsToGenItem $3 }
+  | MITrace NonGenerateModuleItemA { genItemsToGenItem $ map GenModuleItem $ addMITrace $1 $2 }
   | MITrace ConditionalGenerateConstruct { $2 }
   | MITrace LoopGenerateConstruct        { $2 }
 ConditionalGenerateConstruct :: { GenItem }