mirror of https://github.com/zachjs/sv2v.git
13 lines
346 B
Systemverilog
13 lines
346 B
Systemverilog
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module top;
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localparam integer B [4] = { 1, 2, 3, 4 };
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localparam byte C [4] = { 1, 2, 3, 4 };
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localparam bit D [4] = { 1, 2, 3, 4 };
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initial begin
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`define PRINT(X) \
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$display("%b %2d %2d", {X[0], X[1], X[2], X[3]}, $bits(X), $bits(X[0]));
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`PRINT(B);
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`PRINT(C);
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`PRINT(D);
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end
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endmodule
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