mirror of https://github.com/zachjs/sv2v.git
44 lines
753 B
Verilog
44 lines
753 B
Verilog
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`define DISPLAY(expr) \
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$display(`"expr = %b; $bits(expr) = %0d`", expr, $bits(expr));
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`default_nettype wor
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module Example(a, b, c);
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input a, b, c;
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initial begin
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`DISPLAY(a)
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`DISPLAY(b)
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`DISPLAY(c)
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end
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endmodule
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module top;
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wor foo;
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assign foo = 0;
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wor bar;
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assign bar = 1;
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wor o1, o2, o3;
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wor u1, u2, u3;
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and (o1, foo, bar);
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not (o2, o3, foo);
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not (u1, u2, u3);
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wor a, b, c;
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Example e (a, b, c);
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initial begin
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`DISPLAY(foo)
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`DISPLAY(bar)
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`DISPLAY(o1)
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`DISPLAY(o2)
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`DISPLAY(o3)
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`DISPLAY(u1)
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`DISPLAY(u2)
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`DISPLAY(u3)
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`DISPLAY(a)
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`DISPLAY(b)
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`DISPLAY(c)
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end
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endmodule
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