diff --git a/fuzzers/101-bram-config/generate.py b/fuzzers/101-bram-config/generate.py
index f89351db..cb17c458 100644
--- a/fuzzers/101-bram-config/generate.py
+++ b/fuzzers/101-bram-config/generate.py
@@ -74,6 +74,16 @@ def rw_width_tags(segmk, ps, site):
         segmk.add_site_tag(site, '%s_B2' % (param), set_val in (18, ))
 
 
+def write_mode_tags(segmk, ps, site):
+    for param in ["WRITE_MODE_A", "WRITE_MODE_B"]:
+        set_val = verilog.unquote(ps[param])
+        # WRITE_FIRST: no bits set
+        segmk.add_site_tag(
+            site, '%s_READ_FIRST' % (param), set_val == "READ_FIRST")
+        segmk.add_site_tag(
+            site, '%s_NO_CHANGE' % (param), set_val == "NO_CHANGE")
+
+
 def run():
 
     segmk = Segmaker("design.bits", verbose=True)
@@ -92,6 +102,7 @@ def run():
         isenv_tags(segmk, ps, site)
         bus_tags(segmk, ps, site)
         rw_width_tags(segmk, ps, site)
+        write_mode_tags(segmk, ps, site)
 
     def bitfilter(frame, bit):
         # rw_width_tags() aliasing interconnect on large widths
diff --git a/fuzzers/101-bram-config/top.py b/fuzzers/101-bram-config/top.py
index ea5b1e5e..c030673e 100644
--- a/fuzzers/101-bram-config/top.py
+++ b/fuzzers/101-bram-config/top.py
@@ -67,6 +67,8 @@ for loci, (site_type, site) in enumerate(brams):
             'dout': 'dout[  %d +: 8]' % (8 * loci, ),
         }
 
+        write_modes = ["WRITE_FIRST", "READ_FIRST", "NO_CHANGE"]
+
         # Datasheet says 72 is legal in some cases, but think its a copy paste error from BRAM36
         # also 0 and 36 aren't real sizes
         # Bias choice to 18 as its needed to solve certain bits quickly
@@ -82,8 +84,8 @@ for loci, (site_type, site) in enumerate(brams):
             'IS_RSTREGARSTREG_INVERTED': vrandbit(),
             'IS_RSTREGB_INVERTED': vrandbit(),
             'RAM_MODE': '"TDP"',
-            'WRITE_MODE_A': '"WRITE_FIRST"',
-            'WRITE_MODE_B': '"WRITE_FIRST"',
+            'WRITE_MODE_A': verilog.quote(random.choice(write_modes)),
+            'WRITE_MODE_B': verilog.quote(random.choice(write_modes)),
             "DOA_REG": vrandbit(),
             "DOB_REG": vrandbit(),
             "SRVAL_A": vrandbits(18),
diff --git a/minitests/bram_basic/Makefile b/minitests/bram_basic/Makefile
index d5fb4675..ac3e4eed 100644
--- a/minitests/bram_basic/Makefile
+++ b/minitests/bram_basic/Makefile
@@ -40,3 +40,8 @@ build/roi_bramis_bit01.diff:
 build/roi_bram18_width.diff:
 	$(MAKE) -f diff.mk OUT_DIFF=build/roi_bram18_width.diff PRJL=roi_bram18_width_a PRJR=roi_bram18_width_b
 
+
+build/roi_bram18_write_mode.diff:
+	$(MAKE) -f diff.mk OUT_DIFF=build/roi_bram18_write_mode.diff PRJL=roi_bram18_write_mode_a PRJR=roi_bram18_write_mode_b
+
+
diff --git a/minitests/bram_basic/top.v b/minitests/bram_basic/top.v
index 3fd399b3..b8e07ea7 100644
--- a/minitests/bram_basic/top.v
+++ b/minitests/bram_basic/top.v
@@ -280,6 +280,19 @@ module roi_bram18_width_b(input clk, input [255:0] din, output [255:0] dout);
             r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
 endmodule
 
+
+
+module roi_bram18_write_mode_a(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .WRITE_MODE_A("WRITE_FIRST"))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+endmodule
+
+// WRITE_FIRST (default), READ_FIRST, and NO_CHANGE
+module roi_bram18_write_mode_b(input clk, input [255:0] din, output [255:0] dout);
+    ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .WRITE_MODE_A("NO_CHANGE"))
+            r0(.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+endmodule
+
 /******************************************************************************
 Library
 ******************************************************************************/