diff --git a/fuzzers/042-clk-bufg-config/Makefile b/fuzzers/042-clk-bufg-config/Makefile
index 489883b7..86c076a5 100644
--- a/fuzzers/042-clk-bufg-config/Makefile
+++ b/fuzzers/042-clk-bufg-config/Makefile
@@ -1,4 +1,4 @@
-N ?= 40
+N ?= 50
 
 include ../fuzzer.mk
 
diff --git a/fuzzers/042-clk-bufg-config/generate.py b/fuzzers/042-clk-bufg-config/generate.py
index 749831c6..53570591 100644
--- a/fuzzers/042-clk-bufg-config/generate.py
+++ b/fuzzers/042-clk-bufg-config/generate.py
@@ -5,6 +5,13 @@ import json
 from prjxray.segmaker import Segmaker
 
 
+#Decouple interconnect bits from PRESELECT property bits
+def bitfilter(frame, bit):
+    if frame == 7 or frame == 21:
+        return False
+    return True
+
+
 def main():
     segmk = Segmaker("design.bits")
 
@@ -44,7 +51,7 @@ def main():
             segmk.add_site_tag(
                 row['site'], '{}.{}'.format(base_name, tag), 1 ^ row[param])
 
-    segmk.compile()
+    segmk.compile(bitfilter=bitfilter)
     segmk.write()
 
 
diff --git a/fuzzers/Makefile b/fuzzers/Makefile
index 29df6845..39293c13 100644
--- a/fuzzers/Makefile
+++ b/fuzzers/Makefile
@@ -81,8 +81,7 @@ $(eval $(call fuzzer,035-iob-ilogic,005-tilegrid))
 $(eval $(call fuzzer,036-iob-ologic,005-tilegrid))
 $(eval $(call fuzzer,040-clk-hrow-config,005-tilegrid))
 $(eval $(call fuzzer,041-clk-hrow-pips,005-tilegrid))
-# 042 fuzzer is unstable, issue #657
-#$(eval $(call fuzzer,042-clk-bufg-config,005-tilegrid))
+$(eval $(call fuzzer,042-clk-bufg-config,005-tilegrid))
 $(eval $(call fuzzer,043-clk-rebuf-pips,005-tilegrid))
 $(eval $(call fuzzer,048-int-piplist,005-tilegrid))
 $(eval $(call fuzzer,049-int-imux-gfan,048-int-piplist))