From f9793df556c5189b721e149ad83ec7928ccb7f7f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Sun, 26 Nov 2017 02:29:52 +0100 Subject: [PATCH] Cleanups in 070-tileconn Signed-off-by: Clifford Wolf Signed-off-by: Tim 'mithro' Ansell --- fuzzers/070-tileconn/generate.sh | 2 +- fuzzers/070-tileconn/generate.tcl | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/fuzzers/070-tileconn/generate.sh b/fuzzers/070-tileconn/generate.sh index 0f364af6..f639d561 100755 --- a/fuzzers/070-tileconn/generate.sh +++ b/fuzzers/070-tileconn/generate.sh @@ -4,5 +4,5 @@ source ${XRAY_GENHEADER} vivado -mode batch -source ../generate.tcl -# python3 ../generate.py design_*.delta > tilegrid.json +python3 ../generate.py diff --git a/fuzzers/070-tileconn/generate.tcl b/fuzzers/070-tileconn/generate.tcl index 66b6d1db..659bbdd7 100644 --- a/fuzzers/070-tileconn/generate.tcl +++ b/fuzzers/070-tileconn/generate.tcl @@ -1,4 +1,3 @@ -if 0 { create_project -force -part $::env(XRAY_PART) design design read_verilog ../top.v @@ -19,7 +18,6 @@ route_design write_checkpoint -force design.dcp # write_bitstream -force design.bit -} proc print_tile_pair {fp t1 t2} { set t1 [get_tiles $t1]