From f853f6312e5269f29110fedcfafa0da2696b186d Mon Sep 17 00:00:00 2001
From: John McMaster <johndmcmaster@gmail.com>
Date: Mon, 22 Oct 2018 19:47:42 -0700
Subject: [PATCH] 102-bram-data: fuzzer sort of working (interleave issue)

Signed-off-by: John McMaster <johndmcmaster@gmail.com>
---
 fuzzers/102-bram-data/generate.py |  5 +--
 fuzzers/102-bram-data/generate.sh |  2 --
 fuzzers/102-bram-data/top.py      |  5 +--
 prjxray/verilog.py                | 51 +++++++++++++++++++++++++++++++
 4 files changed, 57 insertions(+), 6 deletions(-)
 create mode 100644 prjxray/verilog.py

diff --git a/fuzzers/102-bram-data/generate.py b/fuzzers/102-bram-data/generate.py
index 29a9c10e..3fa86e8a 100644
--- a/fuzzers/102-bram-data/generate.py
+++ b/fuzzers/102-bram-data/generate.py
@@ -8,6 +8,7 @@ from prjxray.segmaker import Segmaker
 c2i = {'0': 0, '1': 1}
 
 segmk = Segmaker("design.bits", verbose=True)
+segmk.set_def_bt('BLOCK_RAM')
 
 print("Loading tags")
 '''
@@ -20,10 +21,10 @@ for l in f:
 
     for i, d in enumerate(pdata):
         # Keep dec convention used on LUT?
-        segmk.add_site_tag(loc, "BRAM.INITP[%04d]" % i, c2i[d])
+        segmk.add_site_tag(loc, "INITP[%04d]" % i, c2i[d])
     for i, d in enumerate(data):
         # Keep dec convention used on LUT?
-        segmk.add_site_tag(loc, "BRAM.INIT[%04d]" % i, c2i[d])
+        segmk.add_site_tag(loc, "INIT[%04d]" % i, c2i[d])
 
 segmk.compile()
 segmk.write()
diff --git a/fuzzers/102-bram-data/generate.sh b/fuzzers/102-bram-data/generate.sh
index 54774bf8..955c41b6 100644
--- a/fuzzers/102-bram-data/generate.sh
+++ b/fuzzers/102-bram-data/generate.sh
@@ -4,8 +4,6 @@ set -ex
 
 source ${XRAY_GENHEADER}
 
-#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
-
 python3 ../top.py >top.v
 vivado -mode batch -source ../generate.tcl
 test -z "$(fgrep CRITICAL vivado.log)"
diff --git a/fuzzers/102-bram-data/top.py b/fuzzers/102-bram-data/top.py
index ae962564..b1c3d9f7 100644
--- a/fuzzers/102-bram-data/top.py
+++ b/fuzzers/102-bram-data/top.py
@@ -15,8 +15,9 @@ SRLC32E_N
 Note: LUT6 was added to try to simplify reduction, although it might not be needed
 '''
 
+import os
 import random
-random.seed(0)
+random.seed(int(os.getenv("SEED"), 16))
 from prjxray import util
 from prjxray import verilog
 import sys
@@ -36,7 +37,7 @@ def gen_bram36():
         yield site_name
 
 
-DUTN = 2
+DUTN = 10
 DIN_N = DUTN * 8
 DOUT_N = DUTN * 8
 
diff --git a/prjxray/verilog.py b/prjxray/verilog.py
new file mode 100644
index 00000000..a6175647
--- /dev/null
+++ b/prjxray/verilog.py
@@ -0,0 +1,51 @@
+import sys
+
+
+def top_harness(DIN_N, DOUT_N, f=sys.stdout):
+    f.write(
+        '''
+module top(input clk, stb, di, output do);
+    localparam integer DIN_N = %d;
+    localparam integer DOUT_N = %d;
+
+    reg [DIN_N-1:0] din;
+    wire [DOUT_N-1:0] dout;
+
+    reg [DIN_N-1:0] din_shr;
+    reg [DOUT_N-1:0] dout_shr;
+
+    always @(posedge clk) begin
+        din_shr <= {din_shr, di};
+        dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+        if (stb) begin
+            din <= din_shr;
+            dout_shr <= dout;
+        end
+    end
+
+    assign do = dout_shr[DOUT_N-1];
+
+    roi roi (
+        .clk(clk),
+        .din(din),
+        .dout(dout)
+    );
+endmodule
+''' % (DIN_N, DOUT_N))
+
+
+def instance(mod, name, ports, params={}, sort=True):
+    # TODO: make this print nicer
+    tosort = sorted if sort else lambda x: x
+    print('    %s' % mod)
+    if len(params):
+        print('        #(')
+        for i, (paramk, paramv) in enumerate(tosort(params.items())):
+            comma = '' if i == len(params) - 1 else ','
+            print('            .%s(%s)%s' % (paramk, paramv, comma))
+        print('        )')
+    print('        %s (' % name)
+    for i, (portk, portv) in enumerate(tosort(ports.items())):
+        comma = '' if i == len(ports) - 1 else ','
+        print('            .%s(%s)%s' % (portk, portv, comma))
+    print('        ));')