diff --git a/minitests/clb_ndi1mux/.gitignore b/minitests/clb_ndi1mux/.gitignore new file mode 100644 index 00000000..82a01aa0 --- /dev/null +++ b/minitests/clb_ndi1mux/.gitignore @@ -0,0 +1,8 @@ +/.Xil +/design/ +/design.bit +/design.bits +/design.dcp +/usage_statistics_webtalk.* +/vivado* +/design.txt diff --git a/minitests/clb_ndi1mux/Makefile b/minitests/clb_ndi1mux/Makefile new file mode 100644 index 00000000..7e47a0e0 --- /dev/null +++ b/minitests/clb_ndi1mux/Makefile @@ -0,0 +1,27 @@ +N := 3 +SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) +SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) + +all: + bash runme.sh + test -z $(fgrep CRITICAL vivado.log) + ${XRAY_SEGPRINT} -z -D design.bits >design.txt + +database: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS)) + +pushdb: + ${XRAY_MERGEDDB} clbll_l seg_clblx.segbits + ${XRAY_MERGEDDB} clbll_r seg_clblx.segbits + ${XRAY_MERGEDDB} clblm_l seg_clblx.segbits + ${XRAY_MERGEDDB} clblm_r seg_clblx.segbits + +$(SPECIMENS_OK): + bash generate.sh $(subst /OK,,$@) + touch $@ + +clean: + rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil + +.PHONY: database pushdb clean + diff --git a/minitests/clb_ndi1mux/README.txt b/minitests/clb_ndi1mux/README.txt new file mode 100644 index 00000000..e3509649 --- /dev/null +++ b/minitests/clb_ndi1mux/README.txt @@ -0,0 +1,12 @@ +Trying to set SLICEM LUT DI1 inputs +These exist for LUTA, LUTB, and LUTC only +Can either be an external signal, another LUT's data input, or another LUT's carry +Note: mux input pattern is irregular + +Result: +Neither external input nor carry input set any unknown bits +Unclear what is going on +Maybe an earlier test incorrectly set these? +Additionally, I could not get BDI1 to activate +Maybe should do a closer pass on BI/DI, which may be easier to trigger + diff --git a/minitests/clb_ndi1mux/runme.sh b/minitests/clb_ndi1mux/runme.sh new file mode 100755 index 00000000..7810c911 --- /dev/null +++ b/minitests/clb_ndi1mux/runme.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +set -ex +# rm -f vivado*.log vivado*.jou +vivado -mode batch -source runme.tcl +${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit +#${XRAY_SEGPRINT} design.bits SLICE_X16Y100 SLICE_X16Y101 SLICE_X16Y102 SLICE_X16Y103 +test -z $(fgrep CRITICAL vivado.log) + diff --git a/minitests/clb_ndi1mux/runme.tcl b/minitests/clb_ndi1mux/runme.tcl new file mode 100644 index 00000000..3a61d1fa --- /dev/null +++ b/minitests/clb_ndi1mux/runme.tcl @@ -0,0 +1,29 @@ +create_project -force -part $::env(XRAY_PART) design design +read_verilog top.v +synth_design -top top + +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] + +create_pblock roi +set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi] +add_cells_to_pblock [get_pblocks roi] [get_cells roi] +# Need to go outside +# SLICE_X12Y100:SLICE_X27Y149 +# resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" +resize_pblock [get_pblocks roi] -add "SLICE_X6Y100:SLICE_X27Y149" + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] + +place_design +route_design + +write_checkpoint -force design.dcp +write_bitstream -force design.bit + diff --git a/minitests/clb_ndi1mux/top.v b/minitests/clb_ndi1mux/top.v new file mode 100644 index 00000000..9ff3ecd3 --- /dev/null +++ b/minitests/clb_ndi1mux/top.v @@ -0,0 +1,326 @@ +/* +SLICEM at the following: +SLICE_XxY* +Where Y any value +x + Always even (ie 100, 102, 104, etc) + In our ROI + x = 6, 8, 10, 12, 14 + +SRL16E: LOC + BEL +SRLC32E: LOC + BEL +RAM64X1S: LOCs but doesn't BEL +*/ + +module top(input clk, stb, di, output do); + localparam integer DIN_N = 256; + localparam integer DOUT_N = 256; + + reg [DIN_N-1:0] din; + wire [DOUT_N-1:0] dout; + + reg [DIN_N-1:0] din_shr; + reg [DOUT_N-1:0] dout_shr; + + always @(posedge clk) begin + din_shr <= {din_shr, di}; + dout_shr <= {dout_shr, din_shr[DIN_N-1]}; + if (stb) begin + din <= din_shr; + dout_shr <= dout; + end + end + + assign do = dout_shr[DOUT_N-1]; + + roi roi ( + .clk(clk), + .din(din), + .dout(dout) + ); +endmodule + +module roi(input clk, input [255:0] din, output [255:0] dout); +`define ALL1 +`ifdef ALL1 + //ok + my_NDI1MUX_NMC31 #(.LOC("SLICE_X6Y100")) + my_NDI1MUX_NMC31(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + /* + //Can't find a valid solution + my_NDI1MUX_NDI1 #(.LOC("SLICE_X6Y101")) + my_NDI1MUX_NDI1(.clk(clk), .din(din[ 8 +: 32]), .dout(dout[ 8 +: 8])); + */ + my_NDI1MUX_NI #(.LOC("SLICE_X6Y102")) + my_NDI1MUX_NI(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); +`endif + +`define SINGLE1 +`ifdef SINGLE1 + //ok + my_BDI1MUX_AI #(.LOC("SLICE_X8Y100"), .BEL("A6LUT")) + my_BDI1MUX_AI(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); + /* + //bad + my_BDI1MUX_BDI1 #(.LOC("SLICE_X8Y101"), .BELO("C6LUT"), .BELI("A6LUT")) + my_BDI1MUX_BDI1(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); + */ + //ok + my_BDI1MUX_BMC31 #(.LOC("SLICE_X8Y102"), .BELO("B6LUT"), .BELI("A6LUT")) + my_BDI1MUX_BMC31(.clk(clk), .din(din[ 80 +: 8]), .dout(dout[ 80 +: 8])); +`endif +endmodule + + +/**************************************************************************** +Tries to set all three muxes at once +****************************************************************************/ + +module my_NDI1MUX_NMC31 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = "SLICE_X6Y100"; + wire [3:0] q31; + + (* LOC=LOC, BEL="D6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutd ( + .Q(dout[0]), + .Q31(q31[3]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); + (* LOC=LOC, BEL="C6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutc ( + .Q(dout[1]), + .Q31(q31[2]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + //.D(din[7])); + .D(q31[3])); + (* LOC=LOC, BEL="B6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutb ( + .Q(dout[2]), + .Q31(q31[1]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + //.D(din[7])); + .D(q31[2])); + (* LOC=LOC, BEL="A6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) luta ( + .Q(dout[3]), + .Q31(q31[0]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + //.D(din[7])); + .D(q31[1])); +endmodule + +/* +//Cannot loc instance 'roi/my_NDI1MUX_NDI1/lutc' at site SLICE_X6Y100, +//Bel does not match with the valid locations at which this inst can be placed + +module my_NDI1MUX_NDI1 (input clk, input [31:0] din, output [7:0] dout); + parameter LOC = "SLICE_X6Y100"; + wire [3:0] q31; + + (* LOC=LOC, BEL="D6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutd ( + .Q(dout[0]), + .Q31(q31[3]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); + (* LOC=LOC, BEL="C6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutc ( + .Q(dout[1]), + .Q31(q31[2]), + .A(din[12:8]), + .CE(din[5]), + .CLK(din[6]), + .D(din[15])); + (* LOC=LOC, BEL="B6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutb ( + .Q(dout[2]), + .Q31(q31[1]), + .A(din[20:16]), + .CE(din[5]), + .CLK(din[6]), + //.D(din[23])); + .D(q31[2])); + (* LOC=LOC, BEL="A6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) luta ( + .Q(dout[3]), + .Q31(q31[0]), + .A(din[28:24]), + .CE(din[5]), + .CLK(din[6]), + //.D(din[31])); + .D(q31[2])); +endmodule +*/ + + +module my_NDI1MUX_NI (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = "SLICE_X6Y100"; + + (* LOC=LOC, BEL="D6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutd ( + .Q(dout[0]), + .Q31(), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); + (* LOC=LOC, BEL="C6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutc ( + .Q(dout[1]), + .Q31(), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); + (* LOC=LOC, BEL="B6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutb ( + .Q(dout[2]), + .Q31(), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); + (* LOC=LOC, BEL="A6LUT" *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) luta ( + .Q(dout[3]), + .Q31(), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); +endmodule + +/**************************************************************************** +Individual mux tests +****************************************************************************/ + +module my_BDI1MUX_AI (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = ""; + parameter BEL="A6LUT"; + + wire mc31c; + + (* LOC=LOC, BEL=BEL *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lut ( + .Q(dout[0]), + .Q31(mc31c), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); +endmodule + +module my_BDI1MUX_BDI1 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = ""; + parameter BELO="C6LUT"; + parameter BELI="A6LUT"; + + wire mc31c; + //wire da = din[6]; + + (* LOC=LOC, BEL=BELO *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutb ( + .Q(dout[0]), + .Q31(mc31c), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); + (* LOC=LOC, BEL=BELI *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) luta ( + .Q(dout[1]), + .Q31(dout[2]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(mc31c)); +endmodule + +//ok +module my_BDI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = ""; + parameter BELO="B6LUT"; + parameter BELI="A6LUT"; + + wire mc31b; + + (* LOC=LOC, BEL=BELO *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) lutb ( + .Q(dout[0]), + .Q31(mc31b), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(din[7])); + (* LOC=LOC, BEL=BELI *) + SRLC32E #( + .INIT(32'h00000000), + .IS_CLK_INVERTED(1'b0) + ) luta ( + .Q(dout[1]), + .Q31(dout[2]), + .A(din[4:0]), + .CE(din[5]), + .CLK(din[6]), + .D(mc31b)); + +endmodule + diff --git a/minitests/clb_ram/top.v b/minitests/clb_ram/top.v index a0daa02b..4fd8e5e2 100644 --- a/minitests/clb_ram/top.v +++ b/minitests/clb_ram/top.v @@ -41,310 +41,6 @@ module top(input clk, stb, di, output do); endmodule module roi(input clk, input [255:0] din, output [255:0] dout); - //ok - my_NDI1MUX_NMC31 #(.LOC("SLICE_X6Y100")) - my_NDI1MUX_NMC31(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - /* - //Can't find a valid solution - my_NDI1MUX_NDI1 #(.LOC("SLICE_X6Y101")) - my_NDI1MUX_NDI1(.clk(clk), .din(din[ 8 +: 32]), .dout(dout[ 8 +: 8])); - */ - my_NDI1MUX_NI #(.LOC("SLICE_X6Y102")) - my_NDI1MUX_NI(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); - - - - /* - //ok - my_BDI1MUX_AI #(.LOC("SLICE_X8Y100"), .BEL("A6LUT")) - my_BDI1MUX_AI(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); - */ - /* - //bad - my_BDI1MUX_BDI1 #(.LOC("SLICE_X8Y101"), .BELO("C6LUT"), .BELI("A6LUT")) - my_BDI1MUX_BDI1(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); - */ - /* - //ok - my_BDI1MUX_BMC31 #(.LOC("SLICE_X8Y102"), .BELO("B6LUT"), .BELI("A6LUT")) - my_BDI1MUX_BMC31(.clk(clk), .din(din[ 80 +: 8]), .dout(dout[ 80 +: 8])); - */ -endmodule - -/**************************************************************************** -Tries to set all three muxes at once -****************************************************************************/ - -module my_NDI1MUX_NMC31 (input clk, input [7:0] din, output [7:0] dout); - parameter LOC = "SLICE_X6Y100"; - wire [3:0] q31; - - (* LOC=LOC, BEL="D6LUT" *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) lutd ( - .Q(dout[0]), - .Q31(q31[3]), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - .D(din[7])); - (* LOC=LOC, BEL="C6LUT" *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) lutc ( - .Q(dout[1]), - .Q31(q31[2]), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - //.D(din[7])); - .D(q31[3])); - (* LOC=LOC, BEL="B6LUT" *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) lutb ( - .Q(dout[2]), - .Q31(q31[1]), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - //.D(din[7])); - .D(q31[2])); - (* LOC=LOC, BEL="A6LUT" *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) luta ( - .Q(dout[3]), - .Q31(q31[0]), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - //.D(din[7])); - .D(q31[1])); -endmodule - -/* -//Cannot loc instance 'roi/my_NDI1MUX_NDI1/lutc' at site SLICE_X6Y100, -//Bel does not match with the valid locations at which this inst can be placed - -module my_NDI1MUX_NDI1 (input clk, input [31:0] din, output [7:0] dout); - parameter LOC = "SLICE_X6Y100"; - wire [3:0] q31; - - (* LOC=LOC, BEL="D6LUT" *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) lutd ( - .Q(dout[0]), - .Q31(q31[3]), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - .D(din[7])); - (* LOC=LOC, BEL="C6LUT" *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) lutc ( - .Q(dout[1]), - .Q31(q31[2]), - .A(din[12:8]), - .CE(din[5]), - .CLK(din[6]), - .D(din[15])); - (* LOC=LOC, BEL="B6LUT" *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) lutb ( - .Q(dout[2]), - .Q31(q31[1]), - .A(din[20:16]), - .CE(din[5]), - .CLK(din[6]), - //.D(din[23])); - .D(q31[2])); - (* LOC=LOC, BEL="A6LUT" *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) luta ( - .Q(dout[3]), - .Q31(q31[0]), - .A(din[28:24]), - .CE(din[5]), - .CLK(din[6]), - //.D(din[31])); - .D(q31[2])); -endmodule -*/ - - -module my_NDI1MUX_NI (input clk, input [7:0] din, output [7:0] dout); - parameter LOC = "SLICE_X6Y100"; - - (* LOC=LOC, BEL="D6LUT" *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) lutd ( - .Q(dout[0]), - .Q31(), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - .D(din[7])); - (* LOC=LOC, BEL="C6LUT" *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) lutc ( - .Q(dout[1]), - .Q31(), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - .D(din[7])); - (* LOC=LOC, BEL="B6LUT" *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) lutb ( - .Q(dout[2]), - .Q31(), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - .D(din[7])); - (* LOC=LOC, BEL="A6LUT" *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) luta ( - .Q(dout[3]), - .Q31(), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - .D(din[7])); -endmodule - -/**************************************************************************** -Individual mux tests -****************************************************************************/ - -module my_BDI1MUX_AI (input clk, input [7:0] din, output [7:0] dout); - parameter LOC = ""; - parameter BEL="A6LUT"; - - wire mc31c; - - (* LOC=LOC, BEL=BEL *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) lut ( - .Q(dout[0]), - .Q31(mc31c), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - .D(din[7])); -endmodule - -module my_BDI1MUX_BDI1 (input clk, input [7:0] din, output [7:0] dout); - parameter LOC = ""; - parameter BELO="C6LUT"; - parameter BELI="A6LUT"; - - wire mc31c; - //wire da = din[6]; - - (* LOC=LOC, BEL=BELO *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) lutb ( - .Q(dout[0]), - .Q31(mc31c), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - .D(din[7])); - (* LOC=LOC, BEL=BELI *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) luta ( - .Q(dout[1]), - .Q31(dout[2]), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - .D(mc31c)); -endmodule - -//ok -module my_BDI1MUX_BMC31 (input clk, input [7:0] din, output [7:0] dout); - parameter LOC = ""; - parameter BELO="B6LUT"; - parameter BELI="A6LUT"; - - wire mc31b; - - (* LOC=LOC, BEL=BELO *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) lutb ( - .Q(dout[0]), - .Q31(mc31b), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - .D(din[7])); - (* LOC=LOC, BEL=BELI *) - SRLC32E #( - .INIT(32'h00000000), - .IS_CLK_INVERTED(1'b0) - ) luta ( - .Q(dout[1]), - .Q31(dout[2]), - .A(din[4:0]), - .CE(din[5]), - .CLK(din[6]), - .D(mc31b)); - -endmodule - - - - - - - - - -/* -Old stuff -This is original file, move mux test out and restore this -*/ - - - - - - - - - - /* //BEL works my_SRLC32E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT")) @@ -357,6 +53,42 @@ This is original file, move mux test out and restore this c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); */ + /* + //BEL works + //No unknown bits + my_SRL16E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT")) + c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + my_SRL16E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT")) + c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + my_SRL16E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT")) + c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + my_SRL16E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT")) + c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + */ + +/* +RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM) +RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM +RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM +RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock +*/ + + /* + my_RAM64M #(.LOC("SLICE_X6Y100")) + my_RAM64M(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + my_RAM64X1S #(.LOC("SLICE_X6Y101")) + my_RAM64X1S(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + my_RAM64X1S_1 #(.LOC("SLICE_X6Y102")) + my_RAM64X1S_1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + my_RAM64X2S #(.LOC("SLICE_X6Y103")) + my_RAM64X2S(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + my_RAM64X1D #(.LOC("SLICE_X6Y104")) + my_RAM64X1D(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); + my_RAM128X1D #(.LOC("SLICE_X6Y105")) + my_RAM128X1D(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); + */ +endmodule + module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout); parameter LOC = ""; parameter BEL="A6LUT"; @@ -376,18 +108,6 @@ module my_SRLC32E (input clk, input [7:0] din, output [7:0] dout); .D(din[7])); endmodule - /* - //BEL works - //No unknown bits - my_SRL16E #(.LOC("SLICE_X6Y100"), .BEL("A6LUT")) - c0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - my_SRL16E #(.LOC("SLICE_X6Y101"), .BEL("B6LUT")) - c1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - my_SRL16E #(.LOC("SLICE_X6Y102"), .BEL("C6LUT")) - c2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - my_SRL16E #(.LOC("SLICE_X6Y103"), .BEL("D6LUT")) - c3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); - */ module my_SRL16E (input clk, input [7:0] din, output [7:0] dout); parameter LOC = ""; @@ -430,28 +150,6 @@ module my_RAM64M (input clk, input [7:0] din, output [7:0] dout); endmodule -/* -RAM64M 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM) -RAM64X1D 64-Deep by 1-Wide Dual Port Static Synchronous RAM -RAM64X1S 64-Deep by 1-Wide Static Synchronous RAM -RAM64X1S_1 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock -*/ - - /* - my_RAM64M #(.LOC("SLICE_X6Y100")) - my_RAM64M(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - my_RAM64X1S #(.LOC("SLICE_X6Y101")) - my_RAM64X1S(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - my_RAM64X1S_1 #(.LOC("SLICE_X6Y102")) - my_RAM64X1S_1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - my_RAM64X2S #(.LOC("SLICE_X6Y103")) - my_RAM64X2S(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); - my_RAM64X1D #(.LOC("SLICE_X6Y104")) - my_RAM64X1D(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); - my_RAM128X1D #(.LOC("SLICE_X6Y105")) - my_RAM128X1D(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); - */ - module my_RAM64X1S (input clk, input [7:0] din, output [7:0] dout); parameter LOC = ""; parameter BEL="A6LUT";