From f2fb1fd145aac0f68e0091ec7b8e6aa7fb1e5135 Mon Sep 17 00:00:00 2001 From: Davide Date: Mon, 19 Feb 2018 17:14:50 +0100 Subject: [PATCH] added database development process to FAQ Signed-off-by: Davide --- .../database development process/overview.rst | 31 +++++++++++++++++++ docs/index.rst | 6 ++++ 2 files changed, 37 insertions(+) create mode 100644 docs/database development process/overview.rst diff --git a/docs/database development process/overview.rst b/docs/database development process/overview.rst new file mode 100644 index 00000000..35f56b82 --- /dev/null +++ b/docs/database development process/overview.rst @@ -0,0 +1,31 @@ +Overview +========= + +SymbiFlow/prjxray/fuzzers/ +^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Fuzzers are things that generate a design, feed it to Vivado, and look at the resulting bitstream to make some conclusion. +This is how the contents of the database are generated. + +The general idea behind fuzzers is to pick some element in the device (say a block RAM or IOB) to target. +If you picked the IOB (no one is working on that yet), you'd write a design that is implemented in a specific IOB. +Then you'd create a program that creates variations of the design (called specimens) that vary the design parameters, for example, changing the configuration of a single pin. + +A lot of this program is TCL that runs inside Vivado to change the design parameters, because it is a bit faster to load in one Verilog model and use TCL to replicate it with varying inputs instead of having different models and loading them individually. + +By looking at all the resulting specimens, you can correlate which bits in which frame correspond to a particular choice in the design. + +Looking at the implemented design in Vivado with "Show Routing Resources" turned on is quite helpful in understanding what all choices exist. + +SymbiFlow/symbiflow-arch-defs +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +This is where we describe the logical components in a device to VPR. +VPR stands for place and route software. + +SymbiFlow/prjxray/tools/ +^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Here, you can find various programs to work with bitstreams, mainly to assist building fuzzers. + +SymbiFlow/minitests/roi_harness +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Shows how to use a bunch of tools together to patch an existing bitstream with hand-crafted FASM (FPGA assembler). + diff --git a/docs/index.rst b/docs/index.rst index 81041af0..b03a7a24 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -21,3 +21,9 @@ to develop a free and open Verilog to bitstream toolchain for these devices. architecture/configuration architecture/bitstream_format architecture/glossary + +.. toctree:: + :maxdepth: 2 + :caption: Database Development Process + + database development process/overview