From f2b0093d119b0ebe07bf20ca94f0aab5913fce59 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Wed, 24 Oct 2018 18:30:59 -0700 Subject: [PATCH] bram: DO_REG, SRVAL, INIT Signed-off-by: John McMaster --- fuzzers/101-bram-config/generate.py | 14 ++++++++++++++ fuzzers/101-bram-config/top.py | 29 ++++++++++++++++++++++++++++- prjxray/segmaker.py | 2 ++ prjxray/verilog.py | 9 +++++++++ 4 files changed, 53 insertions(+), 1 deletion(-) diff --git a/fuzzers/101-bram-config/generate.py b/fuzzers/101-bram-config/generate.py index 9af9b949..22bddcfb 100644 --- a/fuzzers/101-bram-config/generate.py +++ b/fuzzers/101-bram-config/generate.py @@ -6,6 +6,7 @@ from prjxray.segmaker import Segmaker from prjxray import verilog segmk = Segmaker("design.bits", verbose=True) +#segmk.set_def_bt('BLOCK_RAM') print("Loading tags") f = open('params.jl', 'r') @@ -30,6 +31,19 @@ for l in f: ] for param, tagname in ks: segmk.add_site_tag(site, tagname, 1 ^ verilog.parsei(ps[param])) + ''' + parameter DOA_REG = 1'b0; + parameter DOB_REG = 1'b0; + parameter SRVAL_A = 18'b0; + parameter SRVAL_B = 18'b0; + parameter INIT_A = 18'b0; + parameter INIT_B = 18'b0; + ''' + for param, tagname in [('SRVAL_A', 'ZSRVAL_A'), ('SRVAL_B', 'ZSRVAL_B'), + ('INIT_A', 'ZINIT_A'), ('INIT_B', 'ZINIT_B')]: + bitstr = verilog.parse_bitstr(ps[param]) + for i in range(18): + segmk.add_site_tag(site, '%s[%u]' % (param, i), 1 ^ bitstr[i]) segmk.compile() segmk.write() diff --git a/fuzzers/101-bram-config/top.py b/fuzzers/101-bram-config/top.py index 8566bd7d..c9d84b64 100644 --- a/fuzzers/101-bram-config/top.py +++ b/fuzzers/101-bram-config/top.py @@ -65,6 +65,13 @@ def vrandbit(): return "1'b0" +def vrandbits(n): + ret = "%u'b" % n + for _i in range(n): + ret += str(random.randint(0, 1)) + return ret + + for loci, (site_type, site) in enumerate(brams): def place_bram18(): @@ -86,6 +93,12 @@ for loci, (site_type, site) in enumerate(brams): 'RAM_MODE': '"TDP"', 'WRITE_MODE_A': '"WRITE_FIRST"', 'WRITE_MODE_B': '"WRITE_FIRST"', + "DOA_REG": vrandbit(), + "DOB_REG": vrandbit(), + "SRVAL_A": vrandbits(18), + "SRVAL_B": vrandbits(18), + "INIT_A": vrandbits(18), + "INIT_B": vrandbits(18), } return ('my_RAMB18E1', ports, params) @@ -191,6 +204,13 @@ module my_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout); parameter WRITE_MODE_A = "WRITE_FIRST"; parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter DOA_REG = 1'b0; + parameter DOB_REG = 1'b0; + parameter SRVAL_A = 18'b0; + parameter SRVAL_B = 18'b0; + parameter INIT_A = 18'b0; + parameter INIT_B = 18'b0; + ''') print('''\ (* LOC=LOC *) @@ -213,7 +233,14 @@ print( .IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED), .RAM_MODE(RAM_MODE), .WRITE_MODE_A(WRITE_MODE_A), - .WRITE_MODE_B(WRITE_MODE_B) + .WRITE_MODE_B(WRITE_MODE_B), + + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .SRVAL_A(SRVAL_A), + .SRVAL_B(SRVAL_B), + .INIT_A(INIT_A), + .INIT_B(INIT_B) ) ram ( .CLKARDCLK(din[0]), .CLKBWRCLK(din[1]), diff --git a/prjxray/segmaker.py b/prjxray/segmaker.py index 8fc6ddcf..2283ad79 100644 --- a/prjxray/segmaker.py +++ b/prjxray/segmaker.py @@ -124,6 +124,8 @@ class Segmaker: ''' if '"' in site: raise ValueError("Invalid site: %s" % site) + self.verbose and print( + 'segmaker: site %s tag %s = %s' % (site, name, value)) self.site_tags.setdefault(site, dict())[name] = value def add_tile_tag(self, tile, name, value): diff --git a/prjxray/verilog.py b/prjxray/verilog.py index 99a6dde7..9ab29a40 100644 --- a/prjxray/verilog.py +++ b/prjxray/verilog.py @@ -67,3 +67,12 @@ def parsei(s): return 1 else: assert 0, 'FIXME' + + +def parse_bitstr(s): + n, postfix = s.split("'") + n = int(n) + assert postfix[0] == 'b' + bitstr = postfix[1:] + assert len(bitstr) == n + return [int(x) for x in bitstr]