diff --git a/minitests/roi_harness/create_design_json.py b/minitests/roi_harness/create_design_json.py
index 1d127f70..09553d93 100644
--- a/minitests/roi_harness/create_design_json.py
+++ b/minitests/roi_harness/create_design_json.py
@@ -2,6 +2,7 @@ import json
 import csv
 import argparse
 import sys
+import fasm
 from prjxray.db import Database
 from prjxray.roi import Roi
 from prjxray.util import get_db_root
@@ -24,6 +25,7 @@ def main():
     parser.add_argument('--design_txt', required=True)
     parser.add_argument('--design_info_txt', required=True)
     parser.add_argument('--pad_wires', required=True)
+    parser.add_argument('--design_fasm', required=True)
 
     args = parser.parse_args()
 
@@ -51,6 +53,7 @@ def main():
         y2=j['info']['GRID_Y_MAX'],
     )
 
+
     with open(args.pad_wires) as f:
         for l in f:
             parts = l.strip().split(' ')
@@ -70,6 +73,44 @@ def main():
 
             set_port_wires(j['ports'], name, pin, wires_outside_roi)
 
+    frames_in_use = set()
+    for tile in roi.gen_tiles():
+        gridinfo = grid.gridinfo_at_tilename(tile)
+
+        for bit in gridinfo.bits.values():
+            frames_in_use.add(bit.base_address)
+
+    required_features = []
+    for fasm_line in fasm.parse_fasm_filename(args.design_fasm):
+        if fasm_line.annotations:
+            for annotation in fasm_line.annotations:
+                if annotation.name != 'unknown_segment':
+                    continue
+
+                unknown_base_address = int(annotation.value, 0)
+
+                assert unknown_base_address not in frames_in_use, "Found unknown bit in base address 0x{:08x}".format(unknown_base_address)
+
+        if not fasm_line.set_feature:
+            continue
+
+        tile = fasm_line.set_feature.feature.split('.')[0]
+
+        loc = grid.loc_of_tilename(tile)
+        gridinfo = grid.gridinfo_at_tilename(tile)
+
+        base_address_in_roi = False
+        for bit in gridinfo.bits.values():
+            if bit.base_address in frames_in_use:
+                base_address_in_roi = True
+
+        not_in_roi = not roi.tile_in_roi(loc)
+
+        if not_in_roi and base_address_in_roi:
+            required_features.append(fasm_line)
+
+    j['required_features'] = fasm.fasm_tuple_to_string(required_features, canonical=True)
+
     json.dump(j, sys.stdout, indent=2, sort_keys=True)
 
 
diff --git a/minitests/roi_harness/runme.sh b/minitests/roi_harness/runme.sh
index 3435f15f..e72162d8 100755
--- a/minitests/roi_harness/runme.sh
+++ b/minitests/roi_harness/runme.sh
@@ -63,7 +63,11 @@ ${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
 ${XRAY_SEGPRINT} -zd design.bits >design.segp
 python3 ${XRAY_DIR}/utils/bit2fasm.py --verbose design.bit > design.fasm
 python3 ${XRAY_DIR}/utils/fasm2frames.py design.fasm design.frm
-python3 ../create_design_json.py --design_info_txt design_info.txt --design_txt design.txt --pad_wires design_pad_wires.txt > design.json
+python3 ../create_design_json.py \
+    --design_info_txt design_info.txt \
+    --design_txt design.txt \
+    --pad_wires design_pad_wires.txt \
+    --design_fasm design.fasm > design.json
 
 # Hack to get around weird clock error related to clk net not found
 # Remove following lines:
diff --git a/settings/artix7.sh b/settings/artix7.sh
index b6d90a2f..a20f9fec 100644
--- a/settings/artix7.sh
+++ b/settings/artix7.sh
@@ -9,7 +9,7 @@ export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAM
 # These settings must remain in sync
 export XRAY_ROI="SLICE_X0Y100:SLICE_X35Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59 IOB_X0Y100:IOB_X0Y149"
 # Most of CMT X0Y2.
-export XRAY_ROI_GRID_X1="0"
+export XRAY_ROI_GRID_X1="10"
 export XRAY_ROI_GRID_X2="58"
 # Include VBRK / VTERM
 export XRAY_ROI_GRID_Y1="0"