From a2552bf478561abb2d2724095a9b6b45d185cd42 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Wed, 17 Jul 2019 14:34:48 +0200 Subject: [PATCH 01/20] Initial fuzzer for ISERDES only. Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/Makefile | 22 ++ fuzzers/035b-iob-iserdes/bits.dbf | 0 fuzzers/035b-iob-iserdes/generate.py | 170 ++++++++++++++++ fuzzers/035b-iob-iserdes/generate.tcl | 24 +++ fuzzers/035b-iob-iserdes/top.py | 283 ++++++++++++++++++++++++++ 5 files changed, 499 insertions(+) create mode 100644 fuzzers/035b-iob-iserdes/Makefile create mode 100644 fuzzers/035b-iob-iserdes/bits.dbf create mode 100644 fuzzers/035b-iob-iserdes/generate.py create mode 100644 fuzzers/035b-iob-iserdes/generate.tcl create mode 100644 fuzzers/035b-iob-iserdes/top.py diff --git a/fuzzers/035b-iob-iserdes/Makefile b/fuzzers/035b-iob-iserdes/Makefile new file mode 100644 index 00000000..1c3d2d23 --- /dev/null +++ b/fuzzers/035b-iob-iserdes/Makefile @@ -0,0 +1,22 @@ +N := 50 +include ../fuzzer.mk + +database: build/segbits_xiob33.db + +build/segbits_xiob33_msk.rdb: $(SPECIMENS_OK) + #${XRAY_SEGMATCH} -c -1 -m 1 -M 1 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt) + #python3 ~/Work/segmask.py -i build/segbits_xiob33.rdb -o build/segbits_xiob33_msk.rdb -m IN_USE + python3 ~/Work/lms_solver.py -o build/segbits_xiob33_msk.rdb -m IN_USE $$(find -name segdata_*.txt) + +build/segbits_xiob33.db: build/segbits_xiob33_msk.rdb + ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@ + ${XRAY_MASKMERGE} build/mask_xiob33.db $$(find -name segdata_*.txt) + +pushdb: + ${XRAY_MERGEDB} liob33 build/segbits_xiob33.db + ${XRAY_MERGEDB} riob33 build/segbits_xiob33.db + ${XRAY_MERGEDB} mask_liob33 build/mask_xiob33.db + ${XRAY_MERGEDB} mask_riob33 build/mask_xiob33.db + +.PHONY: database pushdb + diff --git a/fuzzers/035b-iob-iserdes/bits.dbf b/fuzzers/035b-iob-iserdes/bits.dbf new file mode 100644 index 00000000..e69de29b diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py new file mode 100644 index 00000000..55f31edf --- /dev/null +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -0,0 +1,170 @@ +#!/usr/bin/env python3 +import json +import re + +from prjxray.segmaker import Segmaker +from prjxray import util +from prjxray import verilog + +segmk = Segmaker("design.bits") + +# Load tags +with open("params.json", "r") as fp: + data = json.load(fp) + +iface_types = ["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"] +data_rates = ["SDR", "DDR"] +data_widths = [2, 3, 4, 5, 6, 7, 8, 10, 14] + +# Output tags +loc_to_tile_site_map = {} +for params in data: + loc = verilog.unquote(params["_LOC"]) + loc = loc.replace("ILOGIC", "IOB") + + get_xy = util.create_xy_fun('IOB_') + x, y = get_xy(loc) + + loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2) + + # Serdes not used at all + if not params["IS_USED"]: + + segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) + + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + + for i in iface_types: + if i == "NETWORKING": + for j in data_rates: + for k in data_widths: + tag = "ISERDES.%s.%s.%s" % (i, j, k) + segmk.add_site_tag(loc, tag, 0) + else: + for j in data_rates: + segmk.add_site_tag(loc, "ISERDES.%s.%s.4" % (i, j), 0) + + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + + for i in range(1, 4+1): + segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0) + + for i in range(1, 4+1): + segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) + + segmk.add_site_tag(loc, "ZINV_D", 0) + + segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) + segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) + + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + + segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0) + + # Serdes used + else: + + segmk.add_site_tag(loc, "ISERDES.IN_USE", 1) + + if "SERDES_MODE" in params: + value = verilog.unquote(params["SERDES_MODE"]) + if value == "MASTER": + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + if value == "SLAVE": + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1) + + iface_type = verilog.unquote(params["INTERFACE_TYPE"]) + data_rate = verilog.unquote(params["DATA_RATE"]) + data_width = int(params["DATA_WIDTH"]) + + for i in iface_types: + for j in data_rates: + for k in data_widths: + tag = "ISERDES.%s.%s.%s" % (i, j, k) + + if i == iface_type: + if j == data_rate: + if k == data_width: + segmk.add_site_tag(loc, tag, 1) + + if "NUM_CE" in params: + value = params["NUM_CE"] + if value == 1: + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + if value == 2: + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1) + + for i in range(1, 4+1): + if ("INIT_Q%d" % i) in params: + segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i]) + + for i in range(1, 4+1): + if ("SRVAL_Q%d" % i) in params: + segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) + + if "IS_D_INVERTED" in params: + segmk.add_site_tag(loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) + + if "DYN_CLKDIV_INV_EN" in params: + value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) + segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE")) + if "DYN_CLK_INV_EN" in params: + value = verilog.unquote(params["DYN_CLK_INV_EN"]) + segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE")) + + # This parameter actually controls muxes used both in ILOGIC and + # ISERDES mode. + if "IOBDELAY" in params: + value = verilog.unquote(params["IOBDELAY"]) + if value == "NONE": + #segmk.add_site_tag(loc, "IOBDELAY_NONE", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.1", 1) + if value == "IBUF": + #segmk.add_site_tag(loc, "IOBDELAY_IBUF", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + if value == "IFD": + #segmk.add_site_tag(loc, "IOBDELAY_IFD" , 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.1", 1) + if value == "BOTH": + #segmk.add_site_tag(loc, "IOBDELAY_BOTH", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + + if "OFB_USED" in params: + value = verilog.unquote(params["OFB_USED"]) + if value == "TRUE": + segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1) + +# Write segments and tags for later check +with open("tags.json", "w") as fp: + tags = {loc_to_tile_site_map[l]: {k: int(v) for k, v in d.items()} for l, d in segmk.site_tags.items()} + json.dump(tags, fp, sort_keys=True, indent=1) + + +def bitfilter(frame_idx, bit_idx): + if frame_idx < 25 or frame_idx > 31: + return False + return True + +segmk.compile(bitfilter=bitfilter) +segmk.write() diff --git a/fuzzers/035b-iob-iserdes/generate.tcl b/fuzzers/035b-iob-iserdes/generate.tcl new file mode 100644 index 00000000..8ba63a89 --- /dev/null +++ b/fuzzers/035b-iob-iserdes/generate.tcl @@ -0,0 +1,24 @@ +set_param general.maxThreads 1 + +create_project -force -part $::env(XRAY_PART) design design +read_verilog top.v +synth_design -top top + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] +set_param tcl.collectionResultDisplayLimit 0 + +set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}] +set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-98}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-109}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-111}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-103}] +set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}] + +place_design +route_design + +write_checkpoint -force design.dcp +write_bitstream -force design.bit diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py new file mode 100644 index 00000000..58ffd3fd --- /dev/null +++ b/fuzzers/035b-iob-iserdes/top.py @@ -0,0 +1,283 @@ +#!/usr/bin/env python3 + +import os, random +random.seed(int(os.getenv("SEED"), 16)) + +import re +import json + +from prjxray import util +from prjxray import verilog +from prjxray.db import Database + +# ============================================================================= + + +def gen_sites(): + db = Database(util.get_db_root()) + grid = db.grid() + + tile_list = [] + for tile_name in sorted(grid.tiles()): + if "IOB33" not in tile_name or "SING" in tile_name: + continue + tile_list.append(tile_name) + + get_xy = util.create_xy_fun('[LR]IOB33_') + tile_list.sort(key=get_xy) + + for iob_tile_name in tile_list: + iob_gridinfo = grid.gridinfo_at_loc( + grid.loc_of_tilename(iob_tile_name)) + + # Find IOI tile adjacent to IOB + for suffix in ["IOI3", "IOI3_TBYTESRC", "IOI3_TBYTETERM"]: + try: + ioi_tile_name = iob_tile_name.replace("IOB33", suffix) + ioi_gridinfo = grid.gridinfo_at_loc( + grid.loc_of_tilename(ioi_tile_name)) + break + except KeyError: + pass + + iob33s = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33S"][0] + iob33m = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33M"][0] + ilogic_s = iob33s.replace("IOB", "ILOGIC") + ilogic_m = iob33m.replace("IOB", "ILOGIC") + + yield iob_tile_name, iob33m, ilogic_m, iob33s, ilogic_s + + +def run(): + + # Get all [LR]IOI3 tiles + tiles = list(gen_sites()) + + # Header + print("// Tile count: %d" % len(tiles)) + print("// Seed: '%s'" % os.getenv("SEED")) + print( + ''' +module top ( + (* CLOCK_BUFFER_TYPE = "NONE" *) + input wire clk1, + (* CLOCK_BUFFER_TYPE = "NONE" *) + input wire clk2, + input wire [{N}:0] di, + output wire [{N}:0] do +); + +wire [{N}:0] di_buf; +wire [{N}:0] do_buf; + '''.format(**{"N": len(tiles) - 1})) + + # LOCes IOBs + data = [] + for i, sites in enumerate(tiles): + tile_name = sites[0] + + # Bottom site + if random.randint(0, 1): + iob_i = sites[1] + iob_o = sites[3] + ilogic = sites[2] + # Top site + else: + iob_i = sites[3] + iob_o = sites[1] + ilogic = sites[4] + + # Site params + params = { + "_LOC": verilog.quote(ilogic), + "IS_USED": int(random.randint(0, 10) > 0), # Make it used more often + "INIT_Q1": random.randint(0, 1), + "INIT_Q2": random.randint(0, 1), + "INIT_Q3": random.randint(0, 1), + "INIT_Q4": random.randint(0, 1), + "SRVAL_Q1": random.randint(0, 1), + "SRVAL_Q2": random.randint(0, 1), + "SRVAL_Q3": random.randint(0, 1), + "SRVAL_Q4": random.randint(0, 1), + "NUM_CE": random.randint(1, 2), + # The following one shows negative correlation (0 - not inverted) + "IS_D_INVERTED": random.randint(0, 1), + # No bits were found for parameters below + #"IS_OCLKB_INVERTED": random.randint(0, 1), + #"IS_OCLK_INVERTED": random.randint(0, 1), + #"IS_CLKDIVP_INVERTED": random.randint(0, 1), + #"IS_CLKDIV_INVERTED": random.randint(0, 1), + #"IS_CLKB_INVERTED": random.randint(0, 1), + #"IS_CLK_INVERTED": random.randint(0, 1), + "DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), + "DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), + "IOBDELAY": verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])), + "OFB_USED": verilog.quote(random.choice(["TRUE"] + ["FALSE"]*9)), # Force more FALSEs + } + + iface_type = random.choice(["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"]) + data_rate = random.choice(["SDR", "DDR"]) + serdes_mode = random.choice(["MASTER", "SLAVE"]) + + params["INTERFACE_TYPE"] = verilog.quote(iface_type) + params["DATA_RATE"] = verilog.quote(data_rate) + params["SERDES_MODE"] = verilog.quote(serdes_mode) + + # Networking mode + if iface_type == "NETWORKING": + data_widths = { + "SDR": [2, 3, 4, 5, 6, 7, 8], + "DDR": [4, 6, 8, 10, 14], + } + params["DATA_WIDTH"] = random.choice(data_widths[data_rate]) + + # Others + else: + params["DATA_WIDTH"] = 4 + + if verilog.unquote(params["OFB_USED"]) == "TRUE": + params["IOBDELAY"] = verilog.quote("NONE") + + # Instantiate cell + param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) + + print('') + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) + print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) + print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) + print( + 'iserdes_single #(%s) iserdes_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' + % (param_str, i, i, i)) + + params["TILE"] = tile_name + data.append(params) + + # Store params + with open("params.json", "w") as fp: + json.dump(data, fp, sort_keys=True, indent=1) + + print( + ''' +endmodule + +(* KEEP, DONT_TOUCH *) +module iserdes_single( + input wire clk1, + input wire clk2, + input wire I, + output wire O +); + +parameter _LOC = ""; +parameter IS_USED = 1; +parameter INTERFACE_TYPE = "NETWORKING"; +parameter DATA_RATE = "DDR"; +parameter DATA_WIDTH = 4; +parameter SERDES_MODE = "MASTER"; +parameter NUM_CE = 2; +parameter INIT_Q1 = 0; +parameter INIT_Q2 = 0; +parameter INIT_Q3 = 0; +parameter INIT_Q4 = 0; +parameter SRVAL_Q1 = 0; +parameter SRVAL_Q2 = 0; +parameter SRVAL_Q3 = 0; +parameter SRVAL_Q4 = 0; +parameter IS_D_INVERTED = 0; +parameter IS_OCLK_INVERTED = 0; +parameter IS_OCLKB_INVERTED = 0; +parameter IS_CLK_INVERTED = 0; +parameter IS_CLKB_INVERTED = 0; +parameter IS_CLKDIV_INVERTED = 0; +parameter IS_CLKDIVP_INVERTED = 0; +parameter DYN_CLKDIV_INV_EN = "FALSE"; +parameter DYN_CLK_INV_EN = "FALSE"; +parameter IOBDELAY = "NONE"; +parameter OFB_USED = "FALSE"; + +(* KEEP, DONT_TOUCH *) +wire [7:0] x; + +generate if (IS_USED) begin + + // Single ISERDES + (* LOC=_LOC, KEEP, DONT_TOUCH *) + ISERDESE2 # + ( + .INTERFACE_TYPE(INTERFACE_TYPE), + .DATA_RATE(DATA_RATE), + .DATA_WIDTH(DATA_WIDTH), + .SERDES_MODE(SERDES_MODE), + .NUM_CE(NUM_CE), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_OCLK_INVERTED(IS_OCLK_INVERTED), + .IS_OCLKB_INVERTED(IS_OCLKB_INVERTED), + .IS_CLK_INVERTED(IS_CLK_INVERTED), + .IS_CLKB_INVERTED(IS_CLKB_INVERTED), + .IS_CLKDIV_INVERTED(IS_CLKDIV_INVERTED), + .IS_CLKDIVP_INVERTED(IS_CLKDIVP_INVERTED), + .INIT_Q1(INIT_Q1), + .INIT_Q2(INIT_Q2), + .INIT_Q3(INIT_Q3), + .INIT_Q4(INIT_Q4), + .SRVAL_Q1(SRVAL_Q1), + .SRVAL_Q2(SRVAL_Q2), + .SRVAL_Q3(SRVAL_Q3), + .SRVAL_Q4(SRVAL_Q4), + .DYN_CLKDIV_INV_EN(DYN_CLKDIV_INV_EN), + .DYN_CLK_INV_EN(DYN_CLK_INV_EN), + .IOBDELAY(IOBDELAY), + .OFB_USED(OFB_USED) + ) + isedres + ( + .D(I), + .DDLY(), + .OFB(), + //.TFB(), + .CE1(), + .CE2(), + .DYNCLKSEL(), + .CLK(clk1), + .CLKB(clk2), + .OCLK(), + .DYNCLKDIVSEL(), + .CLKDIV(), + .CLKDIVP(), + .RST(), + .BITSLIP(), + .O(), + .Q1(x[0]), + .Q2(x[1]), + .Q3(x[2]), + .Q4(x[3]), + .Q5(x[4]), + .Q6(x[5]), + .Q7(x[6]), + .Q8(x[7]), + .SHIFTOUT1(), + .SHIFTOUT2() + ); + +end else begin + + assign x[0] = I; + assign x[1] = I; + assign x[2] = I; + assign x[3] = I; + assign x[4] = I; + assign x[5] = I; + assign x[6] = I; + assign x[7] = I; + +end endgenerate + +// Output +assign O = |x; + +endmodule + ''') + + +run() From 369aa38c6ae2f714c5bbe39546cfc92ddb42cd56 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Mon, 22 Jul 2019 10:52:45 +0200 Subject: [PATCH 02/20] Ran make format-py Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/generate.py | 46 ++++++++++------ fuzzers/035b-iob-iserdes/top.py | 79 ++++++++++++++++++---------- 2 files changed, 79 insertions(+), 46 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index 55f31edf..25da34a9 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -12,8 +12,10 @@ segmk = Segmaker("design.bits") with open("params.json", "r") as fp: data = json.load(fp) -iface_types = ["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"] -data_rates = ["SDR", "DDR"] +iface_types = [ + "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR" +] +data_rates = ["SDR", "DDR"] data_widths = [2, 3, 4, 5, 6, 7, 8, 10, 14] # Output tags @@ -33,7 +35,7 @@ for params in data: segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) for i in iface_types: if i == "NETWORKING": @@ -48,10 +50,10 @@ for params in data: segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) - for i in range(1, 4+1): + for i in range(1, 4 + 1): segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0) - for i in range(1, 4+1): + for i in range(1, 4 + 1): segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) segmk.add_site_tag(loc, "ZINV_D", 0) @@ -75,15 +77,15 @@ for params in data: value = verilog.unquote(params["SERDES_MODE"]) if value == "MASTER": segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) if value == "SLAVE": segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1) iface_type = verilog.unquote(params["INTERFACE_TYPE"]) - data_rate = verilog.unquote(params["DATA_RATE"]) + data_rate = verilog.unquote(params["DATA_RATE"]) data_width = int(params["DATA_WIDTH"]) - + for i in iface_types: for j in data_rates: for k in data_widths: @@ -103,23 +105,28 @@ for params in data: segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1) - for i in range(1, 4+1): + for i in range(1, 4 + 1): if ("INIT_Q%d" % i) in params: - segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i]) + segmk.add_site_tag( + loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i]) - for i in range(1, 4+1): + for i in range(1, 4 + 1): if ("SRVAL_Q%d" % i) in params: - segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) + segmk.add_site_tag( + loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) if "IS_D_INVERTED" in params: - segmk.add_site_tag(loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) + segmk.add_site_tag( + loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) if "DYN_CLKDIV_INV_EN" in params: value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) - segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE")) + segmk.add_site_tag( + loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE")) if "DYN_CLK_INV_EN" in params: value = verilog.unquote(params["DYN_CLK_INV_EN"]) - segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE")) + segmk.add_site_tag( + loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE")) # This parameter actually controls muxes used both in ILOGIC and # ISERDES mode. @@ -157,7 +164,11 @@ for params in data: # Write segments and tags for later check with open("tags.json", "w") as fp: - tags = {loc_to_tile_site_map[l]: {k: int(v) for k, v in d.items()} for l, d in segmk.site_tags.items()} + tags = { + loc_to_tile_site_map[l]: {k: int(v) + for k, v in d.items()} + for l, d in segmk.site_tags.items() + } json.dump(tags, fp, sort_keys=True, indent=1) @@ -166,5 +177,6 @@ def bitfilter(frame_idx, bit_idx): return False return True + segmk.compile(bitfilter=bitfilter) segmk.write() diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index 58ffd3fd..8edee1d6 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -13,7 +13,7 @@ from prjxray.db import Database # ============================================================================= -def gen_sites(): +def gen_sites(): db = Database(util.get_db_root()) grid = db.grid() @@ -78,44 +78,65 @@ wire [{N}:0] do_buf; # Bottom site if random.randint(0, 1): - iob_i = sites[1] - iob_o = sites[3] + iob_i = sites[1] + iob_o = sites[3] ilogic = sites[2] # Top site else: - iob_i = sites[3] - iob_o = sites[1] + iob_i = sites[3] + iob_o = sites[1] ilogic = sites[4] # Site params params = { - "_LOC": verilog.quote(ilogic), - "IS_USED": int(random.randint(0, 10) > 0), # Make it used more often - "INIT_Q1": random.randint(0, 1), - "INIT_Q2": random.randint(0, 1), - "INIT_Q3": random.randint(0, 1), - "INIT_Q4": random.randint(0, 1), - "SRVAL_Q1": random.randint(0, 1), - "SRVAL_Q2": random.randint(0, 1), - "SRVAL_Q3": random.randint(0, 1), - "SRVAL_Q4": random.randint(0, 1), - "NUM_CE": random.randint(1, 2), + "_LOC": + verilog.quote(ilogic), + "IS_USED": + int(random.randint(0, 10) > 0), # Make it used more often + "INIT_Q1": + random.randint(0, 1), + "INIT_Q2": + random.randint(0, 1), + "INIT_Q3": + random.randint(0, 1), + "INIT_Q4": + random.randint(0, 1), + "SRVAL_Q1": + random.randint(0, 1), + "SRVAL_Q2": + random.randint(0, 1), + "SRVAL_Q3": + random.randint(0, 1), + "SRVAL_Q4": + random.randint(0, 1), + "NUM_CE": + random.randint(1, 2), # The following one shows negative correlation (0 - not inverted) - "IS_D_INVERTED": random.randint(0, 1), + "IS_D_INVERTED": + random.randint(0, 1), # No bits were found for parameters below - #"IS_OCLKB_INVERTED": random.randint(0, 1), - #"IS_OCLK_INVERTED": random.randint(0, 1), - #"IS_CLKDIVP_INVERTED": random.randint(0, 1), - #"IS_CLKDIV_INVERTED": random.randint(0, 1), - #"IS_CLKB_INVERTED": random.randint(0, 1), - #"IS_CLK_INVERTED": random.randint(0, 1), - "DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), - "DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), - "IOBDELAY": verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])), - "OFB_USED": verilog.quote(random.choice(["TRUE"] + ["FALSE"]*9)), # Force more FALSEs + #"IS_OCLKB_INVERTED": random.randint(0, 1), + #"IS_OCLK_INVERTED": random.randint(0, 1), + #"IS_CLKDIVP_INVERTED": random.randint(0, 1), + #"IS_CLKDIV_INVERTED": random.randint(0, 1), + #"IS_CLKB_INVERTED": random.randint(0, 1), + #"IS_CLK_INVERTED": random.randint(0, 1), + "DYN_CLKDIV_INV_EN": + verilog.quote(random.choice(["TRUE", "FALSE"])), + "DYN_CLK_INV_EN": + verilog.quote(random.choice(["TRUE", "FALSE"])), + "IOBDELAY": + verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])), + "OFB_USED": + verilog.quote( + random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs } - iface_type = random.choice(["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"]) + iface_type = random.choice( + [ + "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", + "MEMORY_QDR" + ]) data_rate = random.choice(["SDR", "DDR"]) serdes_mode = random.choice(["MASTER", "SLAVE"]) @@ -138,7 +159,7 @@ wire [{N}:0] do_buf; if verilog.unquote(params["OFB_USED"]) == "TRUE": params["IOBDELAY"] = verilog.quote("NONE") - # Instantiate cell + # Instantiate cell param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) print('') From ea0fd9eb8ef0a5d1aa0cff03301d498e412ca1f3 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Mon, 22 Jul 2019 15:57:00 +0200 Subject: [PATCH 03/20] Added fuzzing for chained ISERDES Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/generate.py | 271 +++++++++++++------------- fuzzers/035b-iob-iserdes/generate.tcl | 3 +- fuzzers/035b-iob-iserdes/top.py | 249 ++++++++++++++--------- 3 files changed, 297 insertions(+), 226 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index 25da34a9..70bb8b66 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -19,161 +19,170 @@ data_rates = ["SDR", "DDR"] data_widths = [2, 3, 4, 5, 6, 7, 8, 10, 14] # Output tags -loc_to_tile_site_map = {} -for params in data: - loc = verilog.unquote(params["_LOC"]) - loc = loc.replace("ILOGIC", "IOB") +#loc_to_tile_site_map = {} +for param_list in data: + for params in param_list: + loc = verilog.unquote(params["SITE_LOC"]) + loc = loc.replace("ILOGIC", "IOB") - get_xy = util.create_xy_fun('IOB_') - x, y = get_xy(loc) + get_xy = util.create_xy_fun('IOB_') + x, y = get_xy(loc) - loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2) + #loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2) - # Serdes not used at all - if not params["IS_USED"]: + # Serdes not used at all + if not params["IS_USED"]: - segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) + segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0) + + segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) - segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) - for i in iface_types: - if i == "NETWORKING": + for i in iface_types: + if i == "NETWORKING": + for j in data_rates: + for k in data_widths: + tag = "ISERDES.%s.%s.%s" % (i, j, k) + segmk.add_site_tag(loc, tag, 0) + else: + for j in data_rates: + segmk.add_site_tag(loc, "ISERDES.%s.%s.4" % (i, j), 0) + + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + + for i in range(1, 4 + 1): + segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0) + + for i in range(1, 4 + 1): + segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) + + segmk.add_site_tag(loc, "ZINV_D", 0) + + segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) + segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) + + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + + segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0) + + # Serdes used + else: + + segmk.add_site_tag(loc, "ISERDES.IN_USE", 1) + + if "SHIFTOUT_USED" in params: + if params["CHAINED"]: + value = params["SHIFTOUT_USED"] + segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", value) + + if "SERDES_MODE" in params: + value = verilog.unquote(params["SERDES_MODE"]) + if value == "MASTER": + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + if value == "SLAVE": + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1) + + iface_type = verilog.unquote(params["INTERFACE_TYPE"]) + data_rate = verilog.unquote(params["DATA_RATE"]) + data_width = int(params["DATA_WIDTH"]) + + for i in iface_types: for j in data_rates: for k in data_widths: tag = "ISERDES.%s.%s.%s" % (i, j, k) - segmk.add_site_tag(loc, tag, 0) - else: - for j in data_rates: - segmk.add_site_tag(loc, "ISERDES.%s.%s.4" % (i, j), 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + if i == iface_type: + if j == data_rate: + if k == data_width: + segmk.add_site_tag(loc, tag, 1) - for i in range(1, 4 + 1): - segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0) + if "NUM_CE" in params: + value = params["NUM_CE"] + if value == 1: + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + if value == 2: + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1) - for i in range(1, 4 + 1): - segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) + for i in range(1, 4 + 1): + if ("INIT_Q%d" % i) in params: + segmk.add_site_tag( + loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i]) - segmk.add_site_tag(loc, "ZINV_D", 0) + for i in range(1, 4 + 1): + if ("SRVAL_Q%d" % i) in params: + segmk.add_site_tag( + loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) - segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) - segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) + if "IS_D_INVERTED" in params: + if not params["CHAINED"]: + segmk.add_site_tag( + loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) - segmk.add_site_tag(loc, "IDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.1", 0) - - segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0) - - # Serdes used - else: - - segmk.add_site_tag(loc, "ISERDES.IN_USE", 1) - - if "SERDES_MODE" in params: - value = verilog.unquote(params["SERDES_MODE"]) - if value == "MASTER": - segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) - if value == "SLAVE": - segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1) - - iface_type = verilog.unquote(params["INTERFACE_TYPE"]) - data_rate = verilog.unquote(params["DATA_RATE"]) - data_width = int(params["DATA_WIDTH"]) - - for i in iface_types: - for j in data_rates: - for k in data_widths: - tag = "ISERDES.%s.%s.%s" % (i, j, k) - - if i == iface_type: - if j == data_rate: - if k == data_width: - segmk.add_site_tag(loc, tag, 1) - - if "NUM_CE" in params: - value = params["NUM_CE"] - if value == 1: - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) - if value == 2: - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1) - - for i in range(1, 4 + 1): - if ("INIT_Q%d" % i) in params: + if "DYN_CLKDIV_INV_EN" in params: + value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) segmk.add_site_tag( - loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i]) - - for i in range(1, 4 + 1): - if ("SRVAL_Q%d" % i) in params: + loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE")) + if "DYN_CLK_INV_EN" in params: + value = verilog.unquote(params["DYN_CLK_INV_EN"]) segmk.add_site_tag( - loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) + loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE")) - if "IS_D_INVERTED" in params: - segmk.add_site_tag( - loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) + # This parameter actually controls muxes used both in ILOGIC and + # ISERDES mode. + if "IOBDELAY" in params: + value = verilog.unquote(params["IOBDELAY"]) + if value == "NONE": + #segmk.add_site_tag(loc, "IOBDELAY_NONE", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.1", 1) + if value == "IBUF": + #segmk.add_site_tag(loc, "IOBDELAY_IBUF", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + if value == "IFD": + #segmk.add_site_tag(loc, "IOBDELAY_IFD" , 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.1", 1) + if value == "BOTH": + #segmk.add_site_tag(loc, "IOBDELAY_BOTH", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.1", 0) - if "DYN_CLKDIV_INV_EN" in params: - value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) - segmk.add_site_tag( - loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE")) - if "DYN_CLK_INV_EN" in params: - value = verilog.unquote(params["DYN_CLK_INV_EN"]) - segmk.add_site_tag( - loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE")) - - # This parameter actually controls muxes used both in ILOGIC and - # ISERDES mode. - if "IOBDELAY" in params: - value = verilog.unquote(params["IOBDELAY"]) - if value == "NONE": - #segmk.add_site_tag(loc, "IOBDELAY_NONE", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) - segmk.add_site_tag(loc, "IDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IDELMUXE3.1", 1) - if value == "IBUF": - #segmk.add_site_tag(loc, "IOBDELAY_IBUF", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) - segmk.add_site_tag(loc, "IDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.1", 0) - if value == "IFD": - #segmk.add_site_tag(loc, "IOBDELAY_IFD" , 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) - segmk.add_site_tag(loc, "IDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IDELMUXE3.1", 1) - if value == "BOTH": - #segmk.add_site_tag(loc, "IOBDELAY_BOTH", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) - segmk.add_site_tag(loc, "IDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.1", 0) - - if "OFB_USED" in params: - value = verilog.unquote(params["OFB_USED"]) - if value == "TRUE": - segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1) + if "OFB_USED" in params: + value = verilog.unquote(params["OFB_USED"]) + if value == "TRUE": + segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1) # Write segments and tags for later check -with open("tags.json", "w") as fp: - tags = { - loc_to_tile_site_map[l]: {k: int(v) - for k, v in d.items()} - for l, d in segmk.site_tags.items() - } - json.dump(tags, fp, sort_keys=True, indent=1) +#with open("tags.json", "w") as fp: +# tags = { +# loc_to_tile_site_map[l]: {k: int(v) +# for k, v in d.items()} +# for l, d in segmk.site_tags.items() +# } +# json.dump(tags, fp, sort_keys=True, indent=1) def bitfilter(frame_idx, bit_idx): - if frame_idx < 25 or frame_idx > 31: + if frame_idx < 26 or frame_idx > 31: return False return True diff --git a/fuzzers/035b-iob-iserdes/generate.tcl b/fuzzers/035b-iob-iserdes/generate.tcl index 8ba63a89..1ee1c316 100644 --- a/fuzzers/035b-iob-iserdes/generate.tcl +++ b/fuzzers/035b-iob-iserdes/generate.tcl @@ -1,5 +1,3 @@ -set_param general.maxThreads 1 - create_project -force -part $::env(XRAY_PART) design design read_verilog top.v synth_design -top top @@ -10,6 +8,7 @@ set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] set_param tcl.collectionResultDisplayLimit 0 set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}] +set_property IS_ENABLED 0 [get_drc_checks {NDRV-1}] set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}] set_property IS_ENABLED 0 [get_drc_checks {REQP-98}] set_property IS_ENABLED 0 [get_drc_checks {REQP-109}] diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index 8edee1d6..d5472593 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -47,6 +47,82 @@ def gen_sites(): yield iob_tile_name, iob33m, ilogic_m, iob33s, ilogic_s +def gen_iserdes(loc): + + # Site params + params = { + "SITE_LOC": + verilog.quote(loc), + "IS_USED": + int(random.randint(0, 10) > 0), # Make it used more often + "INIT_Q1": + random.randint(0, 1), + "INIT_Q2": + random.randint(0, 1), + "INIT_Q3": + random.randint(0, 1), + "INIT_Q4": + random.randint(0, 1), + "SRVAL_Q1": + random.randint(0, 1), + "SRVAL_Q2": + random.randint(0, 1), + "SRVAL_Q3": + random.randint(0, 1), + "SRVAL_Q4": + random.randint(0, 1), + "NUM_CE": + random.randint(1, 2), + # The following one shows negative correlation (0 - not inverted) + "IS_D_INVERTED": + random.randint(0, 1), + # No bits were found for parameters below + #"IS_OCLKB_INVERTED": random.randint(0, 1), + #"IS_OCLK_INVERTED": random.randint(0, 1), + #"IS_CLKDIVP_INVERTED": random.randint(0, 1), + #"IS_CLKDIV_INVERTED": random.randint(0, 1), + #"IS_CLKB_INVERTED": random.randint(0, 1), + #"IS_CLK_INVERTED": random.randint(0, 1), + "DYN_CLKDIV_INV_EN": + verilog.quote(random.choice(["TRUE", "FALSE"])), + "DYN_CLK_INV_EN": + verilog.quote(random.choice(["TRUE", "FALSE"])), + "IOBDELAY": + verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])), + "OFB_USED": + verilog.quote( + random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs + } + + iface_type = random.choice( + [ + "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", + "MEMORY_QDR" + ]) + data_rate = random.choice(["SDR", "DDR"]) + serdes_mode = random.choice(["MASTER", "SLAVE"]) + + params["INTERFACE_TYPE"] = verilog.quote(iface_type) + params["DATA_RATE"] = verilog.quote(data_rate) + params["SERDES_MODE"] = verilog.quote(serdes_mode) + + # Networking mode + if iface_type == "NETWORKING": + data_widths = { + "SDR": [2, 3, 4, 5, 6, 7, 8], + "DDR": [4, 6, 8, 10, 14], + } + params["DATA_WIDTH"] = random.choice(data_widths[data_rate]) + + # Others + else: + params["DATA_WIDTH"] = 4 + + if verilog.unquote(params["OFB_USED"]) == "TRUE": + params["IOBDELAY"] = verilog.quote("NONE") + + return params + def run(): @@ -76,103 +152,85 @@ wire [{N}:0] do_buf; for i, sites in enumerate(tiles): tile_name = sites[0] - # Bottom site - if random.randint(0, 1): + # Single ISERDES + if random.randint(0, 5) >= 1: + + # Bottom site + if random.randint(0, 1): + iob_i = sites[1] + iob_o = sites[3] + ilogic = sites[2] + # Top site + else: + iob_i = sites[3] + iob_o = sites[1] + ilogic = sites[4] + + # Generate cell + params = gen_iserdes(ilogic) + + # Instantiate the cell + print('') + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) + print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) + print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) + + param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) + print('iserdes_single #(%s) iserdes_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' % (param_str, i, i, i)) + + params["CHAINED"] = 0 + + data.append([params]) + + # Dual ISERDES chained + else: + iob_i = sites[1] iob_o = sites[3] - ilogic = sites[2] - # Top site - else: - iob_i = sites[3] - iob_o = sites[1] - ilogic = sites[4] + ilogic = [sites[2], sites[4]] + + # Generate cells + params_m = gen_iserdes(ilogic[0]) + params_s = gen_iserdes(ilogic[1]) - # Site params - params = { - "_LOC": - verilog.quote(ilogic), - "IS_USED": - int(random.randint(0, 10) > 0), # Make it used more often - "INIT_Q1": - random.randint(0, 1), - "INIT_Q2": - random.randint(0, 1), - "INIT_Q3": - random.randint(0, 1), - "INIT_Q4": - random.randint(0, 1), - "SRVAL_Q1": - random.randint(0, 1), - "SRVAL_Q2": - random.randint(0, 1), - "SRVAL_Q3": - random.randint(0, 1), - "SRVAL_Q4": - random.randint(0, 1), - "NUM_CE": - random.randint(1, 2), - # The following one shows negative correlation (0 - not inverted) - "IS_D_INVERTED": - random.randint(0, 1), - # No bits were found for parameters below - #"IS_OCLKB_INVERTED": random.randint(0, 1), - #"IS_OCLK_INVERTED": random.randint(0, 1), - #"IS_CLKDIVP_INVERTED": random.randint(0, 1), - #"IS_CLKDIV_INVERTED": random.randint(0, 1), - #"IS_CLKB_INVERTED": random.randint(0, 1), - #"IS_CLK_INVERTED": random.randint(0, 1), - "DYN_CLKDIV_INV_EN": - verilog.quote(random.choice(["TRUE", "FALSE"])), - "DYN_CLK_INV_EN": - verilog.quote(random.choice(["TRUE", "FALSE"])), - "IOBDELAY": - verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])), - "OFB_USED": - verilog.quote( - random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs - } + # Force relevant parameters + params_m["SERDES_MODE"] = verilog.quote("MASTER") + params_m["IS_USED"] = 1 - iface_type = random.choice( - [ - "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", - "MEMORY_QDR" - ]) - data_rate = random.choice(["SDR", "DDR"]) - serdes_mode = random.choice(["MASTER", "SLAVE"]) + params_m["INTERFACE_TYPE"] = verilog.quote("NETWORKING") + params_m["DATA_RATE"] = verilog.quote("DDR") + params_m["DATA_WIDTH"] = random.choice([10, 14]) - params["INTERFACE_TYPE"] = verilog.quote(iface_type) - params["DATA_RATE"] = verilog.quote(data_rate) - params["SERDES_MODE"] = verilog.quote(serdes_mode) + params_s["SERDES_MODE"] = verilog.quote("SLAVE") + params_s["IS_USED"] = 1 - # Networking mode - if iface_type == "NETWORKING": - data_widths = { - "SDR": [2, 3, 4, 5, 6, 7, 8], - "DDR": [4, 6, 8, 10, 14], - } - params["DATA_WIDTH"] = random.choice(data_widths[data_rate]) + params_s["INTERFACE_TYPE"] = params_m["INTERFACE_TYPE"] + params_s["DATA_RATE"] = params_m["DATA_RATE"] + params_s["DATA_WIDTH"] = params_m["DATA_WIDTH"] - # Others - else: - params["DATA_WIDTH"] = 4 + # Instantiate cells + print('') + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) + print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) + print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) - if verilog.unquote(params["OFB_USED"]) == "TRUE": - params["IOBDELAY"] = verilog.quote("NONE") + print('wire o_%03d_m;' % i) + print('wire o_%03d_s;' % i) + print('wire [1:0] sh_%03d;' % i) + print('assign do_buf[%3d] = |q_%03d_m || |q_%03d_s;' % (i, i, i)) + param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_m.items()) + print('iserdes_single #(%s) iserdes_%03d_m (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(q_%03d_m), .shiftout(sh_%03d));' % (param_str, i, i, i, i)) + param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_s.items()) + print('iserdes_single #(%s) iserdes_%03d_s (.clk1(clk1), .clk2(clk2), .O(q_%03d_s), .shiftin(sh_%03d));' % (param_str, i, i, i)) - # Instantiate cell - param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) + params_m["SHIFTOUT_USED"] = 1 - print('') - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) - print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) - print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) - print( - 'iserdes_single #(%s) iserdes_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' - % (param_str, i, i, i)) + params_m["CHAINED"] = 1 + params_s["CHAINED"] = 1 - params["TILE"] = tile_name - data.append(params) + data.append([params_m, params_s]) # Store params with open("params.json", "w") as fp: @@ -187,10 +245,12 @@ module iserdes_single( input wire clk1, input wire clk2, input wire I, - output wire O + output wire O, + input wire [1:0] shiftin, + output wire [1:0] shiftout ); -parameter _LOC = ""; +parameter SITE_LOC = ""; parameter IS_USED = 1; parameter INTERFACE_TYPE = "NETWORKING"; parameter DATA_RATE = "DDR"; @@ -217,13 +277,13 @@ parameter DYN_CLK_INV_EN = "FALSE"; parameter IOBDELAY = "NONE"; parameter OFB_USED = "FALSE"; -(* KEEP, DONT_TOUCH *) wire [7:0] x; +(* KEEP, DONT_TOUCH *) generate if (IS_USED) begin - // Single ISERDES - (* LOC=_LOC, KEEP, DONT_TOUCH *) + // ISERDES + (* LOC=SITE_LOC, KEEP, DONT_TOUCH *) ISERDESE2 # ( .INTERFACE_TYPE(INTERFACE_TYPE), @@ -277,8 +337,10 @@ generate if (IS_USED) begin .Q6(x[5]), .Q7(x[6]), .Q8(x[7]), - .SHIFTOUT1(), - .SHIFTOUT2() + .SHIFTIN1(shiftin[0]), + .SHIFTIN2(shiftin[1]), + .SHIFTOUT1(shiftout[0]), + .SHIFTOUT2(shiftout[1]) ); end else begin @@ -298,6 +360,7 @@ end endgenerate assign O = |x; endmodule + ''') From 44085d34d4b114857c89e3c2c172480c667bd1ad Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Wed, 24 Jul 2019 09:10:09 +0200 Subject: [PATCH 04/20] Moved SDR/DDR out of width setting Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/generate.py | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index 70bb8b66..b7343749 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -42,13 +42,11 @@ for param_list in data: for i in iface_types: if i == "NETWORKING": - for j in data_rates: - for k in data_widths: - tag = "ISERDES.%s.%s.%s" % (i, j, k) - segmk.add_site_tag(loc, tag, 0) + for j in data_widths: + tag = "ISERDES.%s.%s" % (i, j) + segmk.add_site_tag(loc, tag, 0) else: - for j in data_rates: - segmk.add_site_tag(loc, "ISERDES.%s.%s.4" % (i, j), 0) + segmk.add_site_tag(loc, "ISERDES.%s.4" % i, 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) @@ -94,15 +92,16 @@ for param_list in data: data_rate = verilog.unquote(params["DATA_RATE"]) data_width = int(params["DATA_WIDTH"]) - for i in iface_types: - for j in data_rates: - for k in data_widths: - tag = "ISERDES.%s.%s.%s" % (i, j, k) + segmk.add_site_tag(loc, "ISERDES.SDR", int(data_rate == "SDR")) + segmk.add_site_tag(loc, "ISERDES.DDR", int(data_rate == "DDR")) - if i == iface_type: - if j == data_rate: - if k == data_width: - segmk.add_site_tag(loc, tag, 1) + for i in iface_types: + for j in data_widths: + tag = "ISERDES.%s.%s" % (i, j) + + if i == iface_type: + if j == data_width: + segmk.add_site_tag(loc, tag, 1) if "NUM_CE" in params: value = params["NUM_CE"] From 40d3cb558891053a686297291ae4bf9d64728a99 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Thu, 25 Jul 2019 12:08:39 +0200 Subject: [PATCH 05/20] Added fuzzing of IDDR along with ISERDES Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/Makefile | 10 +- fuzzers/035b-iob-iserdes/generate.py | 60 +++++- fuzzers/035b-iob-iserdes/generate.tcl | 1 + fuzzers/035b-iob-iserdes/top.py | 270 +++++++++++++++++++------- 4 files changed, 256 insertions(+), 85 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/Makefile b/fuzzers/035b-iob-iserdes/Makefile index 1c3d2d23..ef4f5fb9 100644 --- a/fuzzers/035b-iob-iserdes/Makefile +++ b/fuzzers/035b-iob-iserdes/Makefile @@ -1,14 +1,14 @@ -N := 50 +N := 20 include ../fuzzer.mk database: build/segbits_xiob33.db -build/segbits_xiob33_msk.rdb: $(SPECIMENS_OK) - #${XRAY_SEGMATCH} -c -1 -m 1 -M 1 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt) +build/segbits_xiob33.rdb: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -c 20 -m 1 -M 1 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt) #python3 ~/Work/segmask.py -i build/segbits_xiob33.rdb -o build/segbits_xiob33_msk.rdb -m IN_USE - python3 ~/Work/lms_solver.py -o build/segbits_xiob33_msk.rdb -m IN_USE $$(find -name segdata_*.txt) + #python3 ~/Work/lms_solver.py -o build/segbits_xiob33_msk.rdb -m IN_USE $$(find -name segdata_*.txt) -build/segbits_xiob33.db: build/segbits_xiob33_msk.rdb +build/segbits_xiob33.db: build/segbits_xiob33.rdb ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@ ${XRAY_MASKMERGE} build/mask_xiob33.db $$(find -name segdata_*.txt) diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index b7343749..bd5978e0 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -30,7 +30,7 @@ for param_list in data: #loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2) - # Serdes not used at all + # Site not used at all if not params["IS_USED"]: segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0) @@ -62,15 +62,17 @@ for param_list in data: segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) - segmk.add_site_tag(loc, "IDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.1", 1) segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0) - # Serdes used - else: + segmk.add_site_tag(loc, "IFF.IN_USE", 0) + + # Site used as ISERDESE2 + elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2": segmk.add_site_tag(loc, "ISERDES.IN_USE", 1) @@ -170,6 +172,50 @@ for param_list in data: if value == "TRUE": segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1) + # Site used as IDDR + elif verilog.unquote(params["BEL_TYPE"]) == "IDDR": + + segmk.add_site_tag(loc, "IFF.IN_USE", 1) + + if "DDR_CLK_EDGE" in params: + value = verilog.unquote(params["DDR_CLK_EDGE"]) + segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.OPPOSITE_EDGE", int(value == "OPPOSITE_EDGE")) + segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.SAME_EDGE", int(value == "SAME_EDGE")) + segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED", int(value == "SAME_EDGE_PIPELINED")) + + if "SRTYPE" in params: + value = verilog.unquote(params["SRTYPE"]) + if value == "ASYNC": + segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 1) + segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 0) + if value == "SYNC": + segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 0) + segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 1) + + if "IDELMUX" in params: + if params["IDELMUX"] == 1: + segmk.add_site_tag(loc, "IDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + else: + segmk.add_site_tag(loc, "IDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.1", 1) + + if "IFFDELMUX" in params: + if params["IFFDELMUX"] == 1: + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) + else: + segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) + + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + + # Should not happen + else: + print("Unknown BEL_TYPE '{}'".format(params["BEL_TYPE"])) + exit(-1) + # Write segments and tags for later check #with open("tags.json", "w") as fp: # tags = { diff --git a/fuzzers/035b-iob-iserdes/generate.tcl b/fuzzers/035b-iob-iserdes/generate.tcl index 1ee1c316..81985aa2 100644 --- a/fuzzers/035b-iob-iserdes/generate.tcl +++ b/fuzzers/035b-iob-iserdes/generate.tcl @@ -14,6 +14,7 @@ set_property IS_ENABLED 0 [get_drc_checks {REQP-98}] set_property IS_ENABLED 0 [get_drc_checks {REQP-109}] set_property IS_ENABLED 0 [get_drc_checks {REQP-111}] set_property IS_ENABLED 0 [get_drc_checks {REQP-103}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}] place_design diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index d5472593..041268dc 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -42,10 +42,20 @@ def gen_sites(): iob33s = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33S"][0] iob33m = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33M"][0] - ilogic_s = iob33s.replace("IOB", "ILOGIC") - ilogic_m = iob33m.replace("IOB", "ILOGIC") - yield iob_tile_name, iob33m, ilogic_m, iob33s, ilogic_s + top_sites = { + "IOB": iob33m, + "ILOGIC": iob33m.replace("IOB", "ILOGIC"), + "IDELAY": iob33m.replace("IOB", "IDELAY"), + } + + bot_sites = { + "IOB": iob33s, + "ILOGIC": iob33s.replace("IOB", "ILOGIC"), + "IDELAY": iob33s.replace("IOB", "IDELAY"), + } + + yield iob_tile_name, top_sites, bot_sites def gen_iserdes(loc): @@ -55,6 +65,10 @@ def gen_iserdes(loc): verilog.quote(loc), "IS_USED": int(random.randint(0, 10) > 0), # Make it used more often + "USE_IDELAY": + random.randint(0, 1), + "BEL_TYPE": + verilog.quote("ISERDESE2"), "INIT_Q1": random.randint(0, 1), "INIT_Q2": @@ -124,6 +138,37 @@ def gen_iserdes(loc): return params +def gen_iddr(loc): + + # Site params + params = { + "SITE_LOC": + verilog.quote(loc), + "IS_USED": + int(random.randint(0, 10) > 0), # Make it used more often + "USE_IDELAY": + random.randint(0, 1), + "BEL_TYPE": + verilog.quote("IDDR"), + "INIT_Q1": + random.randint(0, 1), + "INIT_Q2": + random.randint(0, 1), + "SRTYPE": + verilog.quote(random.choice(["ASYNC", "SYNC"])), + "DDR_CLK_EDGE": + verilog.quote(random.choice(["OPPOSITE_EDGE", "SAME_EDGE", "SAME_EDGE_PIPELINED"])), + } + + if params["USE_IDELAY"]: + params["IDELMUX"] = random.randint(0, 1) + params["IFFDELMUX"] = random.randint(0, 1) + else: + params["IDELMUX"] = 0 + params["IFFDELMUX"] = 0 + + return params + def run(): # Get all [LR]IOI3 tiles @@ -145,6 +190,10 @@ module top ( wire [{N}:0] di_buf; wire [{N}:0] do_buf; + +// IDELAYCTRL +(* KEEP, DONT_TOUCH *) +IDELAYCTRL idelayctrl(); '''.format(**{"N": len(tiles) - 1})) # LOCes IOBs @@ -152,85 +201,100 @@ wire [{N}:0] do_buf; for i, sites in enumerate(tiles): tile_name = sites[0] - # Single ISERDES - if random.randint(0, 5) >= 1: +# # Single ISERDES +# if random.randint(0, 5) >= 1: - # Bottom site - if random.randint(0, 1): - iob_i = sites[1] - iob_o = sites[3] - ilogic = sites[2] - # Top site - else: - iob_i = sites[3] - iob_o = sites[1] - ilogic = sites[4] + # Top sites + if random.randint(0, 1): + this_sites = sites[1] + other_sites = sites[2] - # Generate cell - params = gen_iserdes(ilogic) - - # Instantiate the cell - print('') - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) - print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) - print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) - - param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) - print('iserdes_single #(%s) iserdes_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' % (param_str, i, i, i)) - - params["CHAINED"] = 0 - - data.append([params]) - - # Dual ISERDES chained + # Bottom site else: + this_sites = sites[2] + other_sites = sites[1] - iob_i = sites[1] - iob_o = sites[3] - ilogic = [sites[2], sites[4]] - - # Generate cells - params_m = gen_iserdes(ilogic[0]) - params_s = gen_iserdes(ilogic[1]) + # Generate cell + bel_type = random.choice(["ISERDESE2", "IDDR"]) + if bel_type == "ISERDESE2": + params = gen_iserdes(this_sites["ILOGIC"]) + if bel_type == "IDDR": + params = gen_iddr(this_sites["ILOGIC"]) - # Force relevant parameters - params_m["SERDES_MODE"] = verilog.quote("MASTER") - params_m["IS_USED"] = 1 + params["IDELAY_LOC"] = verilog.quote(this_sites["IDELAY"]) - params_m["INTERFACE_TYPE"] = verilog.quote("NETWORKING") - params_m["DATA_RATE"] = verilog.quote("DDR") - params_m["DATA_WIDTH"] = random.choice([10, 14]) + # Instantiate the cell + print('') + print('// This : ' + " ".join(this_sites.values())) + print('// Other: ' + " ".join(other_sites.values())) + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % this_sites["IOB"]) + print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % other_sites["IOB"]) + print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) - params_s["SERDES_MODE"] = verilog.quote("SLAVE") - params_s["IS_USED"] = 1 + param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) + print('ilogic_single #(%s) ilogic_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' % (param_str, i, i, i)) - params_s["INTERFACE_TYPE"] = params_m["INTERFACE_TYPE"] - params_s["DATA_RATE"] = params_m["DATA_RATE"] - params_s["DATA_WIDTH"] = params_m["DATA_WIDTH"] + params["CHAINED"] = 0 - # Instantiate cells - print('') - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) - print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) - print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) + # Params for the second site + other_params = { + "SITE_LOC": verilog.quote(other_sites["ILOGIC"]), + "IDELAY_LOC": verilog.quote(other_sites["IDELAY"]), + "IS_USED": 0, + } - print('wire o_%03d_m;' % i) - print('wire o_%03d_s;' % i) - print('wire [1:0] sh_%03d;' % i) - print('assign do_buf[%3d] = |q_%03d_m || |q_%03d_s;' % (i, i, i)) - param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_m.items()) - print('iserdes_single #(%s) iserdes_%03d_m (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(q_%03d_m), .shiftout(sh_%03d));' % (param_str, i, i, i, i)) - param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_s.items()) - print('iserdes_single #(%s) iserdes_%03d_s (.clk1(clk1), .clk2(clk2), .O(q_%03d_s), .shiftin(sh_%03d));' % (param_str, i, i, i)) + # Append to data list + data.append([params, other_params]) - params_m["SHIFTOUT_USED"] = 1 - - params_m["CHAINED"] = 1 - params_s["CHAINED"] = 1 - - data.append([params_m, params_s]) +# # Dual ISERDES chained +# else: +# +# iob_i = sites[1] +# iob_o = sites[3] +# ilogic = [sites[2], sites[4]] +# +# # Generate cells +# params_m = gen_iserdes(ilogic[0]) +# params_s = gen_iserdes(ilogic[1]) +# +# # Force relevant parameters +# params_m["SERDES_MODE"] = verilog.quote("MASTER") +# params_m["IS_USED"] = 1 +# +# params_m["INTERFACE_TYPE"] = verilog.quote("NETWORKING") +# params_m["DATA_RATE"] = verilog.quote("DDR") +# params_m["DATA_WIDTH"] = random.choice([10, 14]) +# +# params_s["SERDES_MODE"] = verilog.quote("SLAVE") +# params_s["IS_USED"] = 1 +# +# params_s["INTERFACE_TYPE"] = params_m["INTERFACE_TYPE"] +# params_s["DATA_RATE"] = params_m["DATA_RATE"] +# params_s["DATA_WIDTH"] = params_m["DATA_WIDTH"] +# +# # Instantiate cells +# print('') +# print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) +# print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) +# print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) +# print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) +# +# print('wire o_%03d_m;' % i) +# print('wire o_%03d_s;' % i) +# print('wire [1:0] sh_%03d;' % i) +# print('assign do_buf[%3d] = |q_%03d_m || |q_%03d_s;' % (i, i, i)) +# param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_m.items()) +# print('iserdes_single #(%s) iserdes_%03d_m (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(q_%03d_m), .shiftout(sh_%03d));' % (param_str, i, i, i, i)) +# param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_s.items()) +# print('iserdes_single #(%s) iserdes_%03d_s (.clk1(clk1), .clk2(clk2), .O(q_%03d_s), .shiftin(sh_%03d));' % (param_str, i, i, i)) +# +# params_m["SHIFTOUT_USED"] = 1 +# +# params_m["CHAINED"] = 1 +# params_s["CHAINED"] = 1 +# +# data.append([params_m, params_s]) # Store params with open("params.json", "w") as fp: @@ -241,7 +305,7 @@ wire [{N}:0] do_buf; endmodule (* KEEP, DONT_TOUCH *) -module iserdes_single( +module ilogic_single( input wire clk1, input wire clk2, input wire I, @@ -252,6 +316,11 @@ module iserdes_single( parameter SITE_LOC = ""; parameter IS_USED = 1; +parameter BEL_TYPE = "ISERDESE2"; +parameter IDELAY_LOC = ""; +parameter USE_IDELAY = 0; +parameter IDELMUX = 0; +parameter IFFDELMUX = 0; parameter INTERFACE_TYPE = "NETWORKING"; parameter DATA_RATE = "DDR"; parameter DATA_WIDTH = 4; @@ -276,11 +345,41 @@ parameter DYN_CLKDIV_INV_EN = "FALSE"; parameter DYN_CLK_INV_EN = "FALSE"; parameter IOBDELAY = "NONE"; parameter OFB_USED = "FALSE"; +parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; +parameter SRTYPE = "ASYNC"; wire [7:0] x; +wire ddly; (* KEEP, DONT_TOUCH *) -generate if (IS_USED) begin +generate if (IS_USED && USE_IDELAY) begin + + // IDELAY + (* LOC=IDELAY_LOC, KEEP, DONT_TOUCH *) + IDELAYE2 idelay + ( + .C(clk), + .REGRST(), + .LD(), + .CE(), + .INC(), + .CINVCTRL(), + .CNTVALUEIN(), + .IDATAIN(I), + .DATAIN(), + .LDPIPEEN(), + .DATAOUT(ddly), + .CNTVALUEOUT() + ); + +end else begin + + assign ddly = 0; + +end endgenerate + +(* KEEP, DONT_TOUCH *) +generate if (IS_USED && BEL_TYPE == "ISERDESE2") begin // ISERDES (* LOC=SITE_LOC, KEEP, DONT_TOUCH *) @@ -343,6 +442,31 @@ generate if (IS_USED) begin .SHIFTOUT2(shiftout[1]) ); +end else if (IS_USED && BEL_TYPE == "IDDR") begin + + // IDDR + (* LOC=SITE_LOC, KEEP, DONT_TOUCH *) + IDDR # + ( + .DDR_CLK_EDGE(DDR_CLK_EDGE), + .INIT_Q1(INIT_Q1), + .INIT_Q2(INIT_Q2), + .SRTYPE(SRTYPE) + ) + iddr + ( + .C(clk1), + .CE(), + .D( (IFFDELMUX) ? ddly : I ), + .S(), + .R(), + .Q1(x[0]), + .Q2(x[1]) + ); + + assign x[2] = (IDELMUX) ? ddly : I; + assign x[7:3] = 0; + end else begin assign x[0] = I; From f6aecf0d887d319ebdc96e6edf79b94fb9754abf Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 26 Jul 2019 09:51:47 +0200 Subject: [PATCH 06/20] A lot of modifications and fixups. Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/Makefile | 4 +- fuzzers/035b-iob-iserdes/bits.dbf | 3 + fuzzers/035b-iob-iserdes/generate.py | 176 ++++++++++++------ fuzzers/035b-iob-iserdes/top.py | 265 ++++++++++++--------------- 4 files changed, 240 insertions(+), 208 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/Makefile b/fuzzers/035b-iob-iserdes/Makefile index ef4f5fb9..9254d710 100644 --- a/fuzzers/035b-iob-iserdes/Makefile +++ b/fuzzers/035b-iob-iserdes/Makefile @@ -1,12 +1,10 @@ -N := 20 +N := 50 include ../fuzzer.mk database: build/segbits_xiob33.db build/segbits_xiob33.rdb: $(SPECIMENS_OK) ${XRAY_SEGMATCH} -c 20 -m 1 -M 1 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt) - #python3 ~/Work/segmask.py -i build/segbits_xiob33.rdb -o build/segbits_xiob33_msk.rdb -m IN_USE - #python3 ~/Work/lms_solver.py -o build/segbits_xiob33_msk.rdb -m IN_USE $$(find -name segdata_*.txt) build/segbits_xiob33.db: build/segbits_xiob33.rdb ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@ diff --git a/fuzzers/035b-iob-iserdes/bits.dbf b/fuzzers/035b-iob-iserdes/bits.dbf index e69de29b..45784510 100644 --- a/fuzzers/035b-iob-iserdes/bits.dbf +++ b/fuzzers/035b-iob-iserdes/bits.dbf @@ -0,0 +1,3 @@ +26_99 26_101 26_107 26_109 26_111 26_115 26_121 26_71 27_102 27_108 27_110 27_112 27_70 27_98 28_110 28_67 28_77 28_126 29_67 31_67 31_77 +26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_12 27_16 27_18 27_20 27_26 27_28 27_56 28_02 28_04 28_60 29_01 29_17 29_50 29_60 30_50 30_60 + diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index bd5978e0..b24c9168 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -15,11 +15,17 @@ with open("params.json", "r") as fp: iface_types = [ "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR" ] + data_rates = ["SDR", "DDR"] -data_widths = [2, 3, 4, 5, 6, 7, 8, 10, 14] + +data_widths = { + "SDR": [2, 3, 4, 5, 6, 7, 8], + "DDR": [4, 6, 8, 10, 14], +} + +loc_to_tile_site_map = {} # Output tags -#loc_to_tile_site_map = {} for param_list in data: for params in param_list: loc = verilog.unquote(params["SITE_LOC"]) @@ -28,25 +34,28 @@ for param_list in data: get_xy = util.create_xy_fun('IOB_') x, y = get_xy(loc) - #loc_to_tile_site_map[loc] = params["TILE"] + ".IOB_X0Y%d" % (y % 2) + loc_to_tile_site_map[loc] = params["TILE_NAME"] + ".IOB_Y%d" % (y % 2) # Site not used at all if not params["IS_USED"]: segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0) - + + segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 0) segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) + segmk.add_site_tag(loc, "IFF.IN_USE", 0) segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) for i in iface_types: if i == "NETWORKING": - for j in data_widths: - tag = "ISERDES.%s.%s" % (i, j) - segmk.add_site_tag(loc, tag, 0) + for j in data_rates: + for k in data_widths[j]: + tag = "ISERDES.%s.%s.%s" % (i, j, k) + segmk.add_site_tag(loc, tag, 0) else: - segmk.add_site_tag(loc, "ISERDES.%s.4" % i, 0) + segmk.add_site_tag(loc, "ISERDES.%s.DDR.4" % i, 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) @@ -57,28 +66,35 @@ for param_list in data: for i in range(1, 4 + 1): segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) - segmk.add_site_tag(loc, "ZINV_D", 0) + segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 1) + segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 0) + + segmk.add_site_tag(loc, "ZINV_D", 1) segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) - segmk.add_site_tag(loc, "IDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IDELMUXE3.1", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0) - segmk.add_site_tag(loc, "IFF.IN_USE", 0) +# segmk.add_site_tag(loc, "CE1USED", 0) +# segmk.add_site_tag(loc, "IFF.SUSED", 0) +# segmk.add_site_tag(loc, "IFF.RUSED", 0) - # Site used as ISERDESE2 +# Site used as ISERDESE2 elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2": + segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1) + segmk.add_site_tag(loc, "IFF.IN_USE", 0) segmk.add_site_tag(loc, "ISERDES.IN_USE", 1) if "SHIFTOUT_USED" in params: if params["CHAINED"]: - value = params["SHIFTOUT_USED"] + value = params["SHIFTOUT_USED"] segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", value) if "SERDES_MODE" in params: @@ -94,16 +110,22 @@ for param_list in data: data_rate = verilog.unquote(params["DATA_RATE"]) data_width = int(params["DATA_WIDTH"]) - segmk.add_site_tag(loc, "ISERDES.SDR", int(data_rate == "SDR")) - segmk.add_site_tag(loc, "ISERDES.DDR", int(data_rate == "DDR")) + #segmk.add_site_tag(loc, "ISERDES.SDR", int(data_rate == "SDR")) + #segmk.add_site_tag(loc, "ISERDES.DDR", int(data_rate == "DDR")) for i in iface_types: - for j in data_widths: - tag = "ISERDES.%s.%s" % (i, j) + if i == "NETWORKING": + for j in data_rates: + for k in data_widths[j]: + tag = "ISERDES.%s.%s.%s" % (i, j, k) + if i == iface_type: + if j == data_rate: + if k == data_width: + segmk.add_site_tag(loc, tag, 1) + else: if i == iface_type: - if j == data_width: - segmk.add_site_tag(loc, tag, 1) + segmk.add_site_tag(loc, "ISERDES.%s.DDR.4" % i, 0) if "NUM_CE" in params: value = params["NUM_CE"] @@ -129,6 +151,15 @@ for param_list in data: segmk.add_site_tag( loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) + if "IS_CLKB_INVERTED" in params: + segmk.add_site_tag( + loc, "ISERDES.IS_CLKB_INVERTED", + params["IS_CLKB_INVERTED"]) + + if "IS_CLK_INVERTED" in params: + segmk.add_site_tag( + loc, "ISERDES.IS_CLK_INVERTED", params["IS_CLK_INVERTED"]) + if "DYN_CLKDIV_INV_EN" in params: value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) segmk.add_site_tag( @@ -144,69 +175,91 @@ for param_list in data: value = verilog.unquote(params["IOBDELAY"]) if value == "NONE": #segmk.add_site_tag(loc, "IOBDELAY_NONE", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) - segmk.add_site_tag(loc, "IDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IDELMUXE3.1", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) if value == "IBUF": #segmk.add_site_tag(loc, "IOBDELAY_IBUF", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) - segmk.add_site_tag(loc, "IDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 0) if value == "IFD": #segmk.add_site_tag(loc, "IOBDELAY_IFD" , 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) - segmk.add_site_tag(loc, "IDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IDELMUXE3.1", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) if value == "BOTH": #segmk.add_site_tag(loc, "IOBDELAY_BOTH", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) - segmk.add_site_tag(loc, "IDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 0) if "OFB_USED" in params: value = verilog.unquote(params["OFB_USED"]) - if value == "TRUE": - segmk.add_site_tag(loc, "ISERDES.OFB_USED", 1) + segmk.add_site_tag( + loc, "ISERDES.OFB_USED", int(value == "TRUE")) # Site used as IDDR elif verilog.unquote(params["BEL_TYPE"]) == "IDDR": + segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1) segmk.add_site_tag(loc, "IFF.IN_USE", 1) + segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) if "DDR_CLK_EDGE" in params: value = verilog.unquote(params["DDR_CLK_EDGE"]) - segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.OPPOSITE_EDGE", int(value == "OPPOSITE_EDGE")) - segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.SAME_EDGE", int(value == "SAME_EDGE")) - segmk.add_site_tag(loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED", int(value == "SAME_EDGE_PIPELINED")) + segmk.add_site_tag( + loc, "IFF.DDR_CLK_EDGE.OPPOSITE_EDGE", + int(value == "OPPOSITE_EDGE")) + segmk.add_site_tag( + loc, "IFF.DDR_CLK_EDGE.SAME_EDGE", + int(value == "SAME_EDGE")) + segmk.add_site_tag( + loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED", + int(value == "SAME_EDGE_PIPELINED")) + + # A test + segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 1) + segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 0) if "SRTYPE" in params: value = verilog.unquote(params["SRTYPE"]) if value == "ASYNC": segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 1) - segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 0) + segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 0) if value == "SYNC": segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 0) - segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 1) + segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 1) if "IDELMUX" in params: if params["IDELMUX"] == 1: - segmk.add_site_tag(loc, "IDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 0) else: - segmk.add_site_tag(loc, "IDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IDELMUXE3.1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) if "IFFDELMUX" in params: if params["IFFDELMUX"] == 1: - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) else: - segmk.add_site_tag(loc, "IFFDELMUXE3.0", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.1", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) + + segmk.add_site_tag(loc, "ZINV_D", 0) + + # if "CE1USED" in params: + # segmk.add_site_tag(loc, "CE1USED", params["CE1USED"]) + + # if "SR_MODE" in params: + # value = verilog.unquote(params["SR_MODE"]) + # segmk.add_site_tag(loc, "IFF.SUSED", int(value == "SET")) + # segmk.add_site_tag(loc, "IFF.RUSED", int(value == "RST")) segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) @@ -217,13 +270,16 @@ for param_list in data: exit(-1) # Write segments and tags for later check -#with open("tags.json", "w") as fp: -# tags = { -# loc_to_tile_site_map[l]: {k: int(v) -# for k, v in d.items()} -# for l, d in segmk.site_tags.items() -# } -# json.dump(tags, fp, sort_keys=True, indent=1) +def_tags = {t: 0 for d in segmk.site_tags.values() for t in d.keys()} + +with open("tags.json", "w") as fp: + tags = {} + for l, d in segmk.site_tags.items(): + d1 = dict(def_tags) + d1.update({k: int(v) for k, v in d.items()}) + tags[loc_to_tile_site_map[l]] = d1 + + json.dump(tags, fp, sort_keys=True, indent=1) def bitfilter(frame_idx, bit_idx): diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index 041268dc..e5136fe7 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -44,75 +44,57 @@ def gen_sites(): iob33m = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33M"][0] top_sites = { - "IOB": iob33m, + "IOB": iob33m, "ILOGIC": iob33m.replace("IOB", "ILOGIC"), "IDELAY": iob33m.replace("IOB", "IDELAY"), } bot_sites = { - "IOB": iob33s, + "IOB": iob33s, "ILOGIC": iob33s.replace("IOB", "ILOGIC"), "IDELAY": iob33s.replace("IOB", "IDELAY"), } yield iob_tile_name, top_sites, bot_sites + def gen_iserdes(loc): # Site params params = { - "SITE_LOC": - verilog.quote(loc), - "IS_USED": - int(random.randint(0, 10) > 0), # Make it used more often - "USE_IDELAY": - random.randint(0, 1), - "BEL_TYPE": - verilog.quote("ISERDESE2"), - "INIT_Q1": - random.randint(0, 1), - "INIT_Q2": - random.randint(0, 1), - "INIT_Q3": - random.randint(0, 1), - "INIT_Q4": - random.randint(0, 1), - "SRVAL_Q1": - random.randint(0, 1), - "SRVAL_Q2": - random.randint(0, 1), - "SRVAL_Q3": - random.randint(0, 1), - "SRVAL_Q4": - random.randint(0, 1), - "NUM_CE": - random.randint(1, 2), + "SITE_LOC": verilog.quote(loc), + "USE_IDELAY": random.randint(0, 1), + "BEL_TYPE": verilog.quote("ISERDESE2"), + "INIT_Q1": random.randint(0, 1), + "INIT_Q2": random.randint(0, 1), + "INIT_Q3": random.randint(0, 1), + "INIT_Q4": random.randint(0, 1), + "SRVAL_Q1": random.randint(0, 1), + "SRVAL_Q2": random.randint(0, 1), + "SRVAL_Q3": random.randint(0, 1), + "SRVAL_Q4": random.randint(0, 1), + "NUM_CE": random.randint(1, 2), # The following one shows negative correlation (0 - not inverted) - "IS_D_INVERTED": - random.randint(0, 1), + "IS_D_INVERTED": random.randint(0, 1), # No bits were found for parameters below #"IS_OCLKB_INVERTED": random.randint(0, 1), #"IS_OCLK_INVERTED": random.randint(0, 1), #"IS_CLKDIVP_INVERTED": random.randint(0, 1), #"IS_CLKDIV_INVERTED": random.randint(0, 1), - #"IS_CLKB_INVERTED": random.randint(0, 1), - #"IS_CLK_INVERTED": random.randint(0, 1), - "DYN_CLKDIV_INV_EN": - verilog.quote(random.choice(["TRUE", "FALSE"])), - "DYN_CLK_INV_EN": - verilog.quote(random.choice(["TRUE", "FALSE"])), - "IOBDELAY": - verilog.quote(random.choice(["NONE", "IBUF", "IFD", "BOTH"])), - "OFB_USED": - verilog.quote( + #"IS_CLKB_INVERTED": + #random.randint(0, 1), + #"IS_CLK_INVERTED": + #random.randint(0, 1), + "DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), + "DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), + "IOBDELAY": verilog.quote( + random.choice(["NONE", "IBUF", "IFD", "BOTH"])), + "OFB_USED": verilog.quote( random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs } iface_type = random.choice( - [ - "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", - "MEMORY_QDR" - ]) + ["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"]) data_rate = random.choice(["SDR", "DDR"]) serdes_mode = random.choice(["MASTER", "SLAVE"]) @@ -135,6 +117,9 @@ def gen_iserdes(loc): if verilog.unquote(params["OFB_USED"]) == "TRUE": params["IOBDELAY"] = verilog.quote("NONE") + if serdes_mode == "SLAVE": + params["IS_CLK_INVERTED"] = 0 + return params @@ -144,8 +129,6 @@ def gen_iddr(loc): params = { "SITE_LOC": verilog.quote(loc), - "IS_USED": - int(random.randint(0, 10) > 0), # Make it used more often "USE_IDELAY": random.randint(0, 1), "BEL_TYPE": @@ -157,18 +140,25 @@ def gen_iddr(loc): "SRTYPE": verilog.quote(random.choice(["ASYNC", "SYNC"])), "DDR_CLK_EDGE": - verilog.quote(random.choice(["OPPOSITE_EDGE", "SAME_EDGE", "SAME_EDGE_PIPELINED"])), + verilog.quote( + random.choice( + ["OPPOSITE_EDGE", "SAME_EDGE", "SAME_EDGE_PIPELINED"])), + "CE1USED": + random.randint(0, 1), + "SR_MODE": + verilog.quote(random.choice(["NONE", "SET", "RST"])), } if params["USE_IDELAY"]: - params["IDELMUX"] = random.randint(0, 1) + params["IDELMUX"] = random.randint(0, 1) params["IFFDELMUX"] = random.randint(0, 1) else: - params["IDELMUX"] = 0 + params["IDELMUX"] = 0 params["IFFDELMUX"] = 0 return params + def run(): # Get all [LR]IOI3 tiles @@ -184,6 +174,8 @@ module top ( input wire clk1, (* CLOCK_BUFFER_TYPE = "NONE" *) input wire clk2, + input wire ce, + input wire rst, input wire [{N}:0] di, output wire [{N}:0] do ); @@ -201,100 +193,77 @@ IDELAYCTRL idelayctrl(); for i, sites in enumerate(tiles): tile_name = sites[0] -# # Single ISERDES -# if random.randint(0, 5) >= 1: + # Use site + if random.randint(0, 9) > 0: # Use more often - # Top sites - if random.randint(0, 1): - this_sites = sites[1] - other_sites = sites[2] + # Top sites + if random.randint(0, 1): + this_sites = sites[1] + other_sites = sites[2] + # Bottom sites + else: + this_sites = sites[2] + other_sites = sites[1] - # Bottom site + # Generate cell + bel_types = ["IDDR", "ISERDESE2"] + bel_type = bel_types[int( + random.randint(0, 4) > 0)] # ISERDES more often + if bel_type == "ISERDESE2": + params = gen_iserdes(this_sites["ILOGIC"]) + if bel_type == "IDDR": + params = gen_iddr(this_sites["ILOGIC"]) + + params["IDELAY_LOC"] = verilog.quote(this_sites["IDELAY"]) + params["IS_USED"] = 1 + + # Instantiate the cell + print('') + print('// This : ' + " ".join(this_sites.values())) + print('// Other: ' + " ".join(other_sites.values())) + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % this_sites["IOB"]) + print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % other_sites["IOB"]) + print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) + + param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) + print( + 'ilogic_single #(%s) ilogic_%03d (.clk1(clk1), .clk2(clk2), .ce(ce), .rst(rst), .I(di_buf[%3d]), .O(do_buf[%3d]));' + % (param_str, i, i, i)) + + params["CHAINED"] = 0 + params["TILE_NAME"] = tile_name + + # Params for the second site + other_params = { + "TILE_NAME": tile_name, + "SITE_LOC": verilog.quote(other_sites["ILOGIC"]), + "IDELAY_LOC": verilog.quote(other_sites["IDELAY"]), + "IS_USED": 0, + } + + # Append to data list + data.append([params, other_params]) + + # Don't use sites else: - this_sites = sites[2] - other_sites = sites[1] - # Generate cell - bel_type = random.choice(["ISERDESE2", "IDDR"]) - if bel_type == "ISERDESE2": - params = gen_iserdes(this_sites["ILOGIC"]) - if bel_type == "IDDR": - params = gen_iddr(this_sites["ILOGIC"]) + params_list = [ + { + "TILE_NAME": tile_name, + "SITE_LOC": verilog.quote(sites[1]["ILOGIC"]), + "IDELAY_LOC": verilog.quote(sites[1]["IDELAY"]), + "IS_USED": 0, + }, + { + "TILE_NAME": tile_name, + "SITE_LOC": verilog.quote(sites[2]["ILOGIC"]), + "IDELAY_LOC": verilog.quote(sites[2]["IDELAY"]), + "IS_USED": 0, + } + ] - params["IDELAY_LOC"] = verilog.quote(this_sites["IDELAY"]) - - # Instantiate the cell - print('') - print('// This : ' + " ".join(this_sites.values())) - print('// Other: ' + " ".join(other_sites.values())) - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % this_sites["IOB"]) - print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) - print('(* LOC="%s", KEEP, DONT_TOUCH *)' % other_sites["IOB"]) - print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) - - param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) - print('ilogic_single #(%s) ilogic_%03d (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(do_buf[%3d]));' % (param_str, i, i, i)) - - params["CHAINED"] = 0 - - # Params for the second site - other_params = { - "SITE_LOC": verilog.quote(other_sites["ILOGIC"]), - "IDELAY_LOC": verilog.quote(other_sites["IDELAY"]), - "IS_USED": 0, - } - - # Append to data list - data.append([params, other_params]) - -# # Dual ISERDES chained -# else: -# -# iob_i = sites[1] -# iob_o = sites[3] -# ilogic = [sites[2], sites[4]] -# -# # Generate cells -# params_m = gen_iserdes(ilogic[0]) -# params_s = gen_iserdes(ilogic[1]) -# -# # Force relevant parameters -# params_m["SERDES_MODE"] = verilog.quote("MASTER") -# params_m["IS_USED"] = 1 -# -# params_m["INTERFACE_TYPE"] = verilog.quote("NETWORKING") -# params_m["DATA_RATE"] = verilog.quote("DDR") -# params_m["DATA_WIDTH"] = random.choice([10, 14]) -# -# params_s["SERDES_MODE"] = verilog.quote("SLAVE") -# params_s["IS_USED"] = 1 -# -# params_s["INTERFACE_TYPE"] = params_m["INTERFACE_TYPE"] -# params_s["DATA_RATE"] = params_m["DATA_RATE"] -# params_s["DATA_WIDTH"] = params_m["DATA_WIDTH"] -# -# # Instantiate cells -# print('') -# print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_i) -# print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) -# print('(* LOC="%s", KEEP, DONT_TOUCH *)' % iob_o) -# print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) -# -# print('wire o_%03d_m;' % i) -# print('wire o_%03d_s;' % i) -# print('wire [1:0] sh_%03d;' % i) -# print('assign do_buf[%3d] = |q_%03d_m || |q_%03d_s;' % (i, i, i)) -# param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_m.items()) -# print('iserdes_single #(%s) iserdes_%03d_m (.clk1(clk1), .clk2(clk2), .I(di_buf[%3d]), .O(q_%03d_m), .shiftout(sh_%03d));' % (param_str, i, i, i, i)) -# param_str = ",".join(".%s(%s)" % (k, v) for k, v in params_s.items()) -# print('iserdes_single #(%s) iserdes_%03d_s (.clk1(clk1), .clk2(clk2), .O(q_%03d_s), .shiftin(sh_%03d));' % (param_str, i, i, i)) -# -# params_m["SHIFTOUT_USED"] = 1 -# -# params_m["CHAINED"] = 1 -# params_s["CHAINED"] = 1 -# -# data.append([params_m, params_s]) + data.append(params_list) # Store params with open("params.json", "w") as fp: @@ -308,6 +277,8 @@ endmodule module ilogic_single( input wire clk1, input wire clk2, + input wire ce, + input wire rst, input wire I, output wire O, input wire [1:0] shiftin, @@ -347,8 +318,10 @@ parameter IOBDELAY = "NONE"; parameter OFB_USED = "FALSE"; parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter SRTYPE = "ASYNC"; +parameter CE1USED = 0; +parameter SR_MODE = "NONE"; -wire [7:0] x; +wire [8:0] x; wire ddly; (* KEEP, DONT_TOUCH *) @@ -422,12 +395,13 @@ generate if (IS_USED && BEL_TYPE == "ISERDESE2") begin .CLK(clk1), .CLKB(clk2), .OCLK(), + .OCLKB(), .DYNCLKDIVSEL(), .CLKDIV(), .CLKDIVP(), .RST(), .BITSLIP(), - .O(), + .O(x[8]), .Q1(x[0]), .Q2(x[1]), .Q3(x[2]), @@ -456,16 +430,16 @@ end else if (IS_USED && BEL_TYPE == "IDDR") begin iddr ( .C(clk1), - .CE(), + .CE( (CE1USED) ? ce : 1'hx ), .D( (IFFDELMUX) ? ddly : I ), - .S(), - .R(), + .S( (SR_MODE == "SET") ? rst : 1'd0 ), + .R( (SR_MODE == "RST") ? rst : 1'd0 ), .Q1(x[0]), .Q2(x[1]) ); - assign x[2] = (IDELMUX) ? ddly : I; - assign x[7:3] = 0; + assign x[8] = (IDELMUX) ? ddly : I; + assign x[7:2] = 0; end else begin @@ -477,6 +451,7 @@ end else begin assign x[5] = I; assign x[6] = I; assign x[7] = I; + assign x[8] = I; end endgenerate From d3b6566206d1c25d23ef454e2d49e4dc7932b620 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 26 Jul 2019 13:38:15 +0200 Subject: [PATCH 07/20] Modified dbf file, changed some probabilities. Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/Makefile | 2 +- fuzzers/035b-iob-iserdes/bits.dbf | 9 ++++++--- fuzzers/035b-iob-iserdes/generate.py | 13 +++---------- fuzzers/035b-iob-iserdes/top.py | 4 ++-- 4 files changed, 12 insertions(+), 16 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/Makefile b/fuzzers/035b-iob-iserdes/Makefile index 9254d710..1bc5957e 100644 --- a/fuzzers/035b-iob-iserdes/Makefile +++ b/fuzzers/035b-iob-iserdes/Makefile @@ -1,4 +1,4 @@ -N := 50 +N := 60 include ../fuzzer.mk database: build/segbits_xiob33.db diff --git a/fuzzers/035b-iob-iserdes/bits.dbf b/fuzzers/035b-iob-iserdes/bits.dbf index 45784510..7a400432 100644 --- a/fuzzers/035b-iob-iserdes/bits.dbf +++ b/fuzzers/035b-iob-iserdes/bits.dbf @@ -1,3 +1,6 @@ -26_99 26_101 26_107 26_109 26_111 26_115 26_121 26_71 27_102 27_108 27_110 27_112 27_70 27_98 28_110 28_67 28_77 28_126 29_67 31_67 31_77 -26_15 26_17 26_19 26_25 26_29 26_57 27_06 27_12 27_16 27_18 27_20 27_26 27_28 27_56 28_02 28_04 28_60 29_01 29_17 29_50 29_60 30_50 30_60 - +26_99 27_98 ,IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE +26_99 27_98 ,IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE +26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE +26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE +26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112 +26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26 diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index b24c9168..606eb6ea 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -85,7 +85,7 @@ for param_list in data: # segmk.add_site_tag(loc, "IFF.SUSED", 0) # segmk.add_site_tag(loc, "IFF.RUSED", 0) -# Site used as ISERDESE2 + # Site used as ISERDESE2 elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2": segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1) @@ -110,9 +110,6 @@ for param_list in data: data_rate = verilog.unquote(params["DATA_RATE"]) data_width = int(params["DATA_WIDTH"]) - #segmk.add_site_tag(loc, "ISERDES.SDR", int(data_rate == "SDR")) - #segmk.add_site_tag(loc, "ISERDES.DDR", int(data_rate == "DDR")) - for i in iface_types: if i == "NETWORKING": for j in data_rates: @@ -125,7 +122,7 @@ for param_list in data: segmk.add_site_tag(loc, tag, 1) else: if i == iface_type: - segmk.add_site_tag(loc, "ISERDES.%s.DDR.4" % i, 0) + segmk.add_site_tag(loc, "ISERDES.%s.DDR.4" % i, 1) if "NUM_CE" in params: value = params["NUM_CE"] @@ -174,25 +171,21 @@ for param_list in data: if "IOBDELAY" in params: value = verilog.unquote(params["IOBDELAY"]) if value == "NONE": - #segmk.add_site_tag(loc, "IOBDELAY_NONE", 1) segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) if value == "IBUF": - #segmk.add_site_tag(loc, "IOBDELAY_IBUF", 1) segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) segmk.add_site_tag(loc, "IDELMUXE3.P1", 0) if value == "IFD": - #segmk.add_site_tag(loc, "IOBDELAY_IFD" , 1) segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) if value == "BOTH": - #segmk.add_site_tag(loc, "IOBDELAY_BOTH", 1) segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) @@ -251,7 +244,7 @@ for param_list in data: segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) - segmk.add_site_tag(loc, "ZINV_D", 0) + #segmk.add_site_tag(loc, "ZINV_D", 1) # if "CE1USED" in params: # segmk.add_site_tag(loc, "CE1USED", params["CE1USED"]) diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index e5136fe7..d1690e68 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -194,7 +194,7 @@ IDELAYCTRL idelayctrl(); tile_name = sites[0] # Use site - if random.randint(0, 9) > 0: # Use more often + if random.randint(0, 19) > 0: # Use more often # Top sites if random.randint(0, 1): @@ -208,7 +208,7 @@ IDELAYCTRL idelayctrl(); # Generate cell bel_types = ["IDDR", "ISERDESE2"] bel_type = bel_types[int( - random.randint(0, 4) > 0)] # ISERDES more often + random.randint(0, 19) > 0)] # ISERDES more often if bel_type == "ISERDESE2": params = gen_iserdes(this_sites["ILOGIC"]) if bel_type == "IDDR": From 3ad85e0e4924ac3b8faabb8795c998f36e1539dc Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 26 Jul 2019 15:06:02 +0200 Subject: [PATCH 08/20] Fixed solution for ZINV_D Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/generate.py | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index 606eb6ea..70784d84 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -69,8 +69,6 @@ for param_list in data: segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 1) segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 0) - segmk.add_site_tag(loc, "ZINV_D", 1) - segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) @@ -144,9 +142,7 @@ for param_list in data: loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) if "IS_D_INVERTED" in params: - if not params["CHAINED"]: - segmk.add_site_tag( - loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) + segmk.add_site_tag(loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) if "IS_CLKB_INVERTED" in params: segmk.add_site_tag( @@ -244,8 +240,6 @@ for param_list in data: segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) - #segmk.add_site_tag(loc, "ZINV_D", 1) - # if "CE1USED" in params: # segmk.add_site_tag(loc, "CE1USED", params["CE1USED"]) From 2b87eec19a97bcdc6bbddca9a89e741ae982bf40 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 26 Jul 2019 16:05:36 +0200 Subject: [PATCH 09/20] Added more bits to dbf, added varying of inverters for ISERDES Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/bits.dbf | 4 ++-- fuzzers/035b-iob-iserdes/generate.py | 34 +++++++-------------------- fuzzers/035b-iob-iserdes/generate.tcl | 2 ++ fuzzers/035b-iob-iserdes/top.py | 17 +++++++------- 4 files changed, 22 insertions(+), 35 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/bits.dbf b/fuzzers/035b-iob-iserdes/bits.dbf index 7a400432..1de30d70 100644 --- a/fuzzers/035b-iob-iserdes/bits.dbf +++ b/fuzzers/035b-iob-iserdes/bits.dbf @@ -2,5 +2,5 @@ 26_99 27_98 ,IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE -26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112 -26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26 +26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112 28_126 29_123 29_125 +26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26 28_2 28_4 29_1 diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index 70784d84..cafc248c 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -66,8 +66,8 @@ for param_list in data: for i in range(1, 4 + 1): segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) - segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 1) - segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 0) +# segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 0) +# segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 1) segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) @@ -79,10 +79,6 @@ for param_list in data: segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0) -# segmk.add_site_tag(loc, "CE1USED", 0) -# segmk.add_site_tag(loc, "IFF.SUSED", 0) -# segmk.add_site_tag(loc, "IFF.RUSED", 0) - # Site used as ISERDESE2 elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2": @@ -144,14 +140,14 @@ for param_list in data: if "IS_D_INVERTED" in params: segmk.add_site_tag(loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) - if "IS_CLKB_INVERTED" in params: - segmk.add_site_tag( - loc, "ISERDES.IS_CLKB_INVERTED", - params["IS_CLKB_INVERTED"]) +# if "IS_CLKB_INVERTED" in params: +# segmk.add_site_tag( +# loc, "ISERDES.IS_CLKB_INVERTED", +# params["IS_CLKB_INVERTED"]) - if "IS_CLK_INVERTED" in params: - segmk.add_site_tag( - loc, "ISERDES.IS_CLK_INVERTED", params["IS_CLK_INVERTED"]) +# if "IS_CLK_INVERTED" in params: +# segmk.add_site_tag( +# loc, "ISERDES.IS_CLK_INVERTED", params["IS_CLK_INVERTED"]) if "DYN_CLKDIV_INV_EN" in params: value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) @@ -211,10 +207,6 @@ for param_list in data: loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED", int(value == "SAME_EDGE_PIPELINED")) - # A test - segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 1) - segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 0) - if "SRTYPE" in params: value = verilog.unquote(params["SRTYPE"]) if value == "ASYNC": @@ -240,14 +232,6 @@ for param_list in data: segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) - # if "CE1USED" in params: - # segmk.add_site_tag(loc, "CE1USED", params["CE1USED"]) - - # if "SR_MODE" in params: - # value = verilog.unquote(params["SR_MODE"]) - # segmk.add_site_tag(loc, "IFF.SUSED", int(value == "SET")) - # segmk.add_site_tag(loc, "IFF.RUSED", int(value == "RST")) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) diff --git a/fuzzers/035b-iob-iserdes/generate.tcl b/fuzzers/035b-iob-iserdes/generate.tcl index 81985aa2..d29f3064 100644 --- a/fuzzers/035b-iob-iserdes/generate.tcl +++ b/fuzzers/035b-iob-iserdes/generate.tcl @@ -1,3 +1,5 @@ +set_param general.maxThreads 1 + create_project -force -part $::env(XRAY_PART) design design read_verilog top.v synth_design -top top diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index d1690e68..526ba503 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -74,17 +74,18 @@ def gen_iserdes(loc): "SRVAL_Q3": random.randint(0, 1), "SRVAL_Q4": random.randint(0, 1), "NUM_CE": random.randint(1, 2), + # The following one shows negative correlation (0 - not inverted) "IS_D_INVERTED": random.randint(0, 1), + # No bits were found for parameters below - #"IS_OCLKB_INVERTED": random.randint(0, 1), - #"IS_OCLK_INVERTED": random.randint(0, 1), - #"IS_CLKDIVP_INVERTED": random.randint(0, 1), - #"IS_CLKDIV_INVERTED": random.randint(0, 1), - #"IS_CLKB_INVERTED": - #random.randint(0, 1), - #"IS_CLK_INVERTED": - #random.randint(0, 1), + "IS_OCLKB_INVERTED": random.randint(0, 1), + "IS_OCLK_INVERTED": random.randint(0, 1), + "IS_CLKDIVP_INVERTED": random.randint(0, 1), + "IS_CLKDIV_INVERTED": random.randint(0, 1), + "IS_CLKB_INVERTED": random.randint(0, 1), + "IS_CLK_INVERTED": random.randint(0, 1), + "DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), "DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), "IOBDELAY": verilog.quote( From 10a6547252904a2eaeff43ed4c26a5c2494569d3 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 26 Jul 2019 16:07:09 +0200 Subject: [PATCH 10/20] Ran make format-py Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/generate.py | 3 ++- fuzzers/035b-iob-iserdes/top.py | 1 - 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index cafc248c..e9bd198a 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -138,7 +138,8 @@ for param_list in data: loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) if "IS_D_INVERTED" in params: - segmk.add_site_tag(loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) + segmk.add_site_tag( + loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) # if "IS_CLKB_INVERTED" in params: # segmk.add_site_tag( diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index 526ba503..691d3f0f 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -85,7 +85,6 @@ def gen_iserdes(loc): "IS_CLKDIV_INVERTED": random.randint(0, 1), "IS_CLKB_INVERTED": random.randint(0, 1), "IS_CLK_INVERTED": random.randint(0, 1), - "DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), "DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), "IOBDELAY": verilog.quote( From 01c1b0e23ce5e19580d3f343b33b6dd814046d71 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Mon, 5 Aug 2019 10:43:26 +0200 Subject: [PATCH 11/20] Added filtering of some overlapping bits (by frame idx). Executing logic put in a function. Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/generate.py | 410 ++++++++++++++------------- 1 file changed, 209 insertions(+), 201 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index e9bd198a..29cdad47 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -6,12 +6,6 @@ from prjxray.segmaker import Segmaker from prjxray import util from prjxray import verilog -segmk = Segmaker("design.bits") - -# Load tags -with open("params.json", "r") as fp: - data = json.load(fp) - iface_types = [ "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR" ] @@ -23,242 +17,256 @@ data_widths = { "DDR": [4, 6, 8, 10, 14], } -loc_to_tile_site_map = {} -# Output tags -for param_list in data: - for params in param_list: - loc = verilog.unquote(params["SITE_LOC"]) - loc = loc.replace("ILOGIC", "IOB") +def run(): - get_xy = util.create_xy_fun('IOB_') - x, y = get_xy(loc) + segmk = Segmaker("design.bits") - loc_to_tile_site_map[loc] = params["TILE_NAME"] + ".IOB_Y%d" % (y % 2) + # Load tags + with open("params.json", "r") as fp: + data = json.load(fp) - # Site not used at all - if not params["IS_USED"]: + loc_to_tile_site_map = {} - segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0) + # Output tags + for param_list in data: + for params in param_list: + loc = verilog.unquote(params["SITE_LOC"]) + loc = loc.replace("ILOGIC", "IOB") - segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 0) - segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) - segmk.add_site_tag(loc, "IFF.IN_USE", 0) + get_xy = util.create_xy_fun('IOB_') + x, y = get_xy(loc) - segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + loc_to_tile_site_map[loc] = params["TILE_NAME"] + ".IOB_Y%d" % ( + y % 2) - for i in iface_types: - if i == "NETWORKING": - for j in data_rates: - for k in data_widths[j]: - tag = "ISERDES.%s.%s.%s" % (i, j, k) - segmk.add_site_tag(loc, tag, 0) - else: - segmk.add_site_tag(loc, "ISERDES.%s.DDR.4" % i, 0) + # Site not used at all + if not params["IS_USED"]: - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0) - for i in range(1, 4 + 1): - segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0) + segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 0) + segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) + segmk.add_site_tag(loc, "IFF.IN_USE", 0) - for i in range(1, 4 + 1): - segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) -# segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 0) -# segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 1) + for i in iface_types: + if i == "NETWORKING": + for j in data_rates: + for k in data_widths[j]: + tag = "ISERDES.%s.%s.%s" % (i, j, k) + segmk.add_site_tag(loc, tag, 0) + else: + segmk.add_site_tag(loc, "ISERDES.%s.DDR.4" % i, 0) - segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) - segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) - segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) - segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) + for i in range(1, 4 + 1): + segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0) - segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0) + for i in range(1, 4 + 1): + segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) - # Site used as ISERDESE2 - elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2": + # segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 0) + # segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 1) - segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1) - segmk.add_site_tag(loc, "IFF.IN_USE", 0) - segmk.add_site_tag(loc, "ISERDES.IN_USE", 1) + segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) + segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) - if "SHIFTOUT_USED" in params: - if params["CHAINED"]: - value = params["SHIFTOUT_USED"] - segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", value) + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) - if "SERDES_MODE" in params: - value = verilog.unquote(params["SERDES_MODE"]) - if value == "MASTER": - segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) - if value == "SLAVE": - segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) - segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1) + segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0) - iface_type = verilog.unquote(params["INTERFACE_TYPE"]) - data_rate = verilog.unquote(params["DATA_RATE"]) - data_width = int(params["DATA_WIDTH"]) + # Site used as ISERDESE2 + elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2": - for i in iface_types: - if i == "NETWORKING": - for j in data_rates: - for k in data_widths[j]: - tag = "ISERDES.%s.%s.%s" % (i, j, k) + segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1) + segmk.add_site_tag(loc, "IFF.IN_USE", 0) + segmk.add_site_tag(loc, "ISERDES.IN_USE", 1) - if i == iface_type: - if j == data_rate: - if k == data_width: - segmk.add_site_tag(loc, tag, 1) - else: - if i == iface_type: - segmk.add_site_tag(loc, "ISERDES.%s.DDR.4" % i, 1) + if "SHIFTOUT_USED" in params: + if params["CHAINED"]: + value = params["SHIFTOUT_USED"] + segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", value) - if "NUM_CE" in params: - value = params["NUM_CE"] - if value == 1: - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) - if value == 2: - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1) + if "SERDES_MODE" in params: + value = verilog.unquote(params["SERDES_MODE"]) + if value == "MASTER": + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + if value == "SLAVE": + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1) - for i in range(1, 4 + 1): - if ("INIT_Q%d" % i) in params: + iface_type = verilog.unquote(params["INTERFACE_TYPE"]) + data_rate = verilog.unquote(params["DATA_RATE"]) + data_width = int(params["DATA_WIDTH"]) + + for i in iface_types: + if i == "NETWORKING": + for j in data_rates: + for k in data_widths[j]: + tag = "ISERDES.%s.%s.%s" % (i, j, k) + + if i == iface_type: + if j == data_rate: + if k == data_width: + segmk.add_site_tag(loc, tag, 1) + else: + if i == iface_type: + segmk.add_site_tag(loc, "ISERDES.%s.DDR.4" % i, 1) + + if "NUM_CE" in params: + value = params["NUM_CE"] + if value == 1: + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + if value == 2: + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1) + + for i in range(1, 4 + 1): + if ("INIT_Q%d" % i) in params: + segmk.add_site_tag( + loc, "IFF.ZINIT_Q%d" % i, + not params["INIT_Q%d" % i]) + + for i in range(1, 4 + 1): + if ("SRVAL_Q%d" % i) in params: + segmk.add_site_tag( + loc, "IFF.ZSRVAL_Q%d" % i, + not params["SRVAL_Q%d" % i]) + + if "IS_D_INVERTED" in params: segmk.add_site_tag( - loc, "IFF.ZINIT_Q%d" % i, not params["INIT_Q%d" % i]) + loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) - for i in range(1, 4 + 1): - if ("SRVAL_Q%d" % i) in params: + # if "IS_CLKB_INVERTED" in params: + # segmk.add_site_tag( + # loc, "ISERDES.IS_CLKB_INVERTED", + # params["IS_CLKB_INVERTED"]) + + # if "IS_CLK_INVERTED" in params: + # segmk.add_site_tag( + # loc, "ISERDES.IS_CLK_INVERTED", params["IS_CLK_INVERTED"]) + + if "DYN_CLKDIV_INV_EN" in params: + value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) segmk.add_site_tag( - loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) + loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE")) + if "DYN_CLK_INV_EN" in params: + value = verilog.unquote(params["DYN_CLK_INV_EN"]) + segmk.add_site_tag( + loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE")) - if "IS_D_INVERTED" in params: - segmk.add_site_tag( - loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) + # This parameter actually controls muxes used both in ILOGIC and + # ISERDES mode. + if "IOBDELAY" in params: + value = verilog.unquote(params["IOBDELAY"]) + if value == "NONE": + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) + if value == "IBUF": + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 0) + if value == "IFD": + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) + if value == "BOTH": + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 0) -# if "IS_CLKB_INVERTED" in params: -# segmk.add_site_tag( -# loc, "ISERDES.IS_CLKB_INVERTED", -# params["IS_CLKB_INVERTED"]) + if "OFB_USED" in params: + value = verilog.unquote(params["OFB_USED"]) + segmk.add_site_tag( + loc, "ISERDES.OFB_USED", int(value == "TRUE")) -# if "IS_CLK_INVERTED" in params: -# segmk.add_site_tag( -# loc, "ISERDES.IS_CLK_INVERTED", params["IS_CLK_INVERTED"]) + # Site used as IDDR + elif verilog.unquote(params["BEL_TYPE"]) == "IDDR": - if "DYN_CLKDIV_INV_EN" in params: - value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) - segmk.add_site_tag( - loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE")) - if "DYN_CLK_INV_EN" in params: - value = verilog.unquote(params["DYN_CLK_INV_EN"]) - segmk.add_site_tag( - loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE")) + segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1) + segmk.add_site_tag(loc, "IFF.IN_USE", 1) + segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) - # This parameter actually controls muxes used both in ILOGIC and - # ISERDES mode. - if "IOBDELAY" in params: - value = verilog.unquote(params["IOBDELAY"]) - if value == "NONE": - segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) - segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) - segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) - if value == "IBUF": - segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) - segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.P1", 0) - if value == "IFD": - segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) - segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) - segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) - if value == "BOTH": - segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) - segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.P1", 0) + if "DDR_CLK_EDGE" in params: + value = verilog.unquote(params["DDR_CLK_EDGE"]) + segmk.add_site_tag( + loc, "IFF.DDR_CLK_EDGE.OPPOSITE_EDGE", + int(value == "OPPOSITE_EDGE")) + segmk.add_site_tag( + loc, "IFF.DDR_CLK_EDGE.SAME_EDGE", + int(value == "SAME_EDGE")) + segmk.add_site_tag( + loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED", + int(value == "SAME_EDGE_PIPELINED")) - if "OFB_USED" in params: - value = verilog.unquote(params["OFB_USED"]) - segmk.add_site_tag( - loc, "ISERDES.OFB_USED", int(value == "TRUE")) + if "SRTYPE" in params: + value = verilog.unquote(params["SRTYPE"]) + if value == "ASYNC": + segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 1) + segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 0) + if value == "SYNC": + segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 0) + segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 1) - # Site used as IDDR - elif verilog.unquote(params["BEL_TYPE"]) == "IDDR": + if "IDELMUX" in params: + if params["IDELMUX"] == 1: + segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 0) + else: + segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) - segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1) - segmk.add_site_tag(loc, "IFF.IN_USE", 1) - segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) + if "IFFDELMUX" in params: + if params["IFFDELMUX"] == 1: + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) + else: + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) - if "DDR_CLK_EDGE" in params: - value = verilog.unquote(params["DDR_CLK_EDGE"]) - segmk.add_site_tag( - loc, "IFF.DDR_CLK_EDGE.OPPOSITE_EDGE", - int(value == "OPPOSITE_EDGE")) - segmk.add_site_tag( - loc, "IFF.DDR_CLK_EDGE.SAME_EDGE", - int(value == "SAME_EDGE")) - segmk.add_site_tag( - loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED", - int(value == "SAME_EDGE_PIPELINED")) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) - if "SRTYPE" in params: - value = verilog.unquote(params["SRTYPE"]) - if value == "ASYNC": - segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 1) - segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 0) - if value == "SYNC": - segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 0) - segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 1) + # Should not happen + else: + print("Unknown BEL_TYPE '{}'".format(params["BEL_TYPE"])) + exit(-1) - if "IDELMUX" in params: - if params["IDELMUX"] == 1: - segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) - segmk.add_site_tag(loc, "IDELMUXE3.P1", 0) - else: - segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) - segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) + # Write segments and tags for later check + def_tags = {t: 0 for d in segmk.site_tags.values() for t in d.keys()} - if "IFFDELMUX" in params: - if params["IFFDELMUX"] == 1: - segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) - segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) - else: - segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) - segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) + with open("tags.json", "w") as fp: + tags = {} + for l, d in segmk.site_tags.items(): + d1 = dict(def_tags) + d1.update({k: int(v) for k, v in d.items()}) + tags[loc_to_tile_site_map[l]] = d1 - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + json.dump(tags, fp, sort_keys=True, indent=1) - # Should not happen - else: - print("Unknown BEL_TYPE '{}'".format(params["BEL_TYPE"])) - exit(-1) + def bitfilter(frame_idx, bit_idx): + if frame_idx < 26 or frame_idx > 29: + return False + return True -# Write segments and tags for later check -def_tags = {t: 0 for d in segmk.site_tags.values() for t in d.keys()} - -with open("tags.json", "w") as fp: - tags = {} - for l, d in segmk.site_tags.items(): - d1 = dict(def_tags) - d1.update({k: int(v) for k, v in d.items()}) - tags[loc_to_tile_site_map[l]] = d1 - - json.dump(tags, fp, sort_keys=True, indent=1) + segmk.compile(bitfilter=bitfilter) + segmk.write() -def bitfilter(frame_idx, bit_idx): - if frame_idx < 26 or frame_idx > 31: - return False - return True - - -segmk.compile(bitfilter=bitfilter) -segmk.write() +if __name__ == "__main__": + run() From b02c0f5135150ead1bf40794265207feb8bdd736 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Mon, 25 Nov 2019 12:48:21 +0100 Subject: [PATCH 12/20] Removed aliasing with some PIP bits. Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/bits.dbf | 4 ++-- fuzzers/035b-iob-iserdes/generate.tcl | 1 + fuzzers/035b-iob-iserdes/top.py | 6 ++++-- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/bits.dbf b/fuzzers/035b-iob-iserdes/bits.dbf index 1de30d70..7a400432 100644 --- a/fuzzers/035b-iob-iserdes/bits.dbf +++ b/fuzzers/035b-iob-iserdes/bits.dbf @@ -2,5 +2,5 @@ 26_99 27_98 ,IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE -26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112 28_126 29_123 29_125 -26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26 28_2 28_4 29_1 +26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112 +26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26 diff --git a/fuzzers/035b-iob-iserdes/generate.tcl b/fuzzers/035b-iob-iserdes/generate.tcl index d29f3064..c5751862 100644 --- a/fuzzers/035b-iob-iserdes/generate.tcl +++ b/fuzzers/035b-iob-iserdes/generate.tcl @@ -18,6 +18,7 @@ set_property IS_ENABLED 0 [get_drc_checks {REQP-111}] set_property IS_ENABLED 0 [get_drc_checks {REQP-103}] set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-105}] place_design route_design diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index 691d3f0f..ffe962ef 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -226,10 +226,12 @@ IDELAYCTRL idelayctrl(); print('(* LOC="%s", KEEP, DONT_TOUCH *)' % other_sites["IOB"]) print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) + clk1_conn = random.choice(["clk1", ""]) + param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) print( - 'ilogic_single #(%s) ilogic_%03d (.clk1(clk1), .clk2(clk2), .ce(ce), .rst(rst), .I(di_buf[%3d]), .O(do_buf[%3d]));' - % (param_str, i, i, i)) + 'ilogic_single #(%s) ilogic_%03d (.clk1(%s), .clk2(clk2), .ce(ce), .rst(rst), .I(di_buf[%3d]), .O(do_buf[%3d]));' + % (param_str, i, clk1_conn, i, i)) params["CHAINED"] = 0 params["TILE_NAME"] = tile_name From ebf88a84301ea5d1faf29b77a305e67bb0cbe733 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Mon, 25 Nov 2019 13:24:14 +0100 Subject: [PATCH 13/20] Disabled renaming ILOGIC to IOB, code formatting. Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/generate.py | 1 - 1 file changed, 1 deletion(-) diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index 29cdad47..5e407f38 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -32,7 +32,6 @@ def run(): for param_list in data: for params in param_list: loc = verilog.unquote(params["SITE_LOC"]) - loc = loc.replace("ILOGIC", "IOB") get_xy = util.create_xy_fun('IOB_') x, y = get_xy(loc) From e68b3083d4431274422b14b998463d03a51f94e0 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Mon, 25 Nov 2019 16:13:49 +0100 Subject: [PATCH 14/20] Added changing of clock inverters / updated bits.dbf Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/bits.dbf | 14 +++++--- fuzzers/035b-iob-iserdes/generate.py | 49 ++++++++++++++++------------ fuzzers/035b-iob-iserdes/top.py | 12 ++++--- 3 files changed, 46 insertions(+), 29 deletions(-) diff --git a/fuzzers/035b-iob-iserdes/bits.dbf b/fuzzers/035b-iob-iserdes/bits.dbf index 7a400432..63a90990 100644 --- a/fuzzers/035b-iob-iserdes/bits.dbf +++ b/fuzzers/035b-iob-iserdes/bits.dbf @@ -1,6 +1,12 @@ -26_99 27_98 ,IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE -26_99 27_98 ,IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE -26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE -26_29 27_28 ,IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE +IOI3.ILOGIC_Y0.IDELMUXE3.P0 ^ IOI3.ILOGIC_Y0.IDELMUXE3.P1 +IOI3.ILOGIC_Y0.IFFDELMUXE3.P0 ^ IOI3.ILOGIC_Y0.IFFDELMUXE3.P1 +IOI3.ILOGIC_Y1.IDELMUXE3.P0 ^ IOI3.ILOGIC_Y1.IDELMUXE3.P1 +IOI3.ILOGIC_Y1.IFFDELMUXE3.P0 ^ IOI3.ILOGIC_Y1.IFFDELMUXE3.P1 + +26_99 27_98 ,IOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE +26_99 27_98 ,IOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE +26_29 27_28 ,IOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE +26_29 27_28 ,IOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE + 26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112 26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26 diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index 5e407f38..c2ac5e39 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -34,7 +34,7 @@ def run(): loc = verilog.unquote(params["SITE_LOC"]) get_xy = util.create_xy_fun('IOB_') - x, y = get_xy(loc) + x, y = get_xy(loc.replace("ILOGIC", "IOB")) loc_to_tile_site_map[loc] = params["TILE_NAME"] + ".IOB_Y%d" % ( y % 2) @@ -60,8 +60,8 @@ def run(): else: segmk.add_site_tag(loc, "ISERDES.%s.DDR.4" % i, 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0) for i in range(1, 4 + 1): segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0) @@ -112,6 +112,7 @@ def run(): for j in data_rates: for k in data_widths[j]: tag = "ISERDES.%s.%s.%s" % (i, j, k) + val = 0 if i == iface_type: if j == data_rate: @@ -124,11 +125,11 @@ def run(): if "NUM_CE" in params: value = params["NUM_CE"] if value == 1: - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0) if value == 2: - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 0) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 1) for i in range(1, 4 + 1): if ("INIT_Q%d" % i) in params: @@ -142,18 +143,15 @@ def run(): loc, "IFF.ZSRVAL_Q%d" % i, not params["SRVAL_Q%d" % i]) - if "IS_D_INVERTED" in params: - segmk.add_site_tag( - loc, "ZINV_D", int(params["IS_D_INVERTED"] == 0)) - - # if "IS_CLKB_INVERTED" in params: - # segmk.add_site_tag( - # loc, "ISERDES.IS_CLKB_INVERTED", - # params["IS_CLKB_INVERTED"]) - - # if "IS_CLK_INVERTED" in params: - # segmk.add_site_tag( - # loc, "ISERDES.IS_CLK_INVERTED", params["IS_CLK_INVERTED"]) + for inv in ["CLK", "CLKB", "OCLK", "OCLKB", "CLKDIV", + "CLKDIVP"]: + if "IS_{}_INVERTED".format(inv) in params: + segmk.add_site_tag( + loc, "ISERDES.INV_{}".format(inv), + params["IS_{}_INVERTED".format(inv)]) + segmk.add_site_tag( + loc, "ISERDES.ZINV_{}".format(inv), + not params["IS_{}_INVERTED".format(inv)]) if "DYN_CLKDIV_INV_EN" in params: value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) @@ -238,8 +236,17 @@ def run(): segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.1", 1) - segmk.add_site_tag(loc, "ISERDES.NUM_CE.2", 0) + for inv in ["C", "D"]: + if "IS_{}_INVERTED".format(inv) in params: + segmk.add_site_tag( + loc, "INV_{}".format(inv), + params["IS_{}_INVERTED".format(inv)]) + segmk.add_site_tag( + loc, "ZINV_{}".format(inv), + not params["IS_{}_INVERTED".format(inv)]) + + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0) # Should not happen else: diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index ffe962ef..b1ff01ea 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -117,9 +117,6 @@ def gen_iserdes(loc): if verilog.unquote(params["OFB_USED"]) == "TRUE": params["IOBDELAY"] = verilog.quote("NONE") - if serdes_mode == "SLAVE": - params["IS_CLK_INVERTED"] = 0 - return params @@ -147,6 +144,10 @@ def gen_iddr(loc): random.randint(0, 1), "SR_MODE": verilog.quote(random.choice(["NONE", "SET", "RST"])), + "IS_C_INVERTED": + random.randint(0, 1), + "IS_D_INVERTED": + random.randint(0, 1), } if params["USE_IDELAY"]: @@ -208,7 +209,7 @@ IDELAYCTRL idelayctrl(); # Generate cell bel_types = ["IDDR", "ISERDESE2"] bel_type = bel_types[int( - random.randint(0, 19) > 0)] # ISERDES more often + random.randint(0, 2) > 0)] # ISERDES more often if bel_type == "ISERDESE2": params = gen_iserdes(this_sites["ILOGIC"]) if bel_type == "IDDR": @@ -322,6 +323,7 @@ parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; parameter SRTYPE = "ASYNC"; parameter CE1USED = 0; parameter SR_MODE = "NONE"; +parameter IS_C_INVERTED = 0; wire [8:0] x; wire ddly; @@ -424,6 +426,8 @@ end else if (IS_USED && BEL_TYPE == "IDDR") begin (* LOC=SITE_LOC, KEEP, DONT_TOUCH *) IDDR # ( + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), .DDR_CLK_EDGE(DDR_CLK_EDGE), .INIT_Q1(INIT_Q1), .INIT_Q2(INIT_Q2), From d83a7031e5e808fb1691440e3b54fd39e6ea63a1 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Mon, 25 Nov 2019 16:26:22 +0100 Subject: [PATCH 15/20] Code formatting. Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/top.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index b1ff01ea..e1add6cb 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -443,7 +443,7 @@ end else if (IS_USED && BEL_TYPE == "IDDR") begin .Q1(x[0]), .Q2(x[1]) ); - + assign x[8] = (IDELMUX) ? ddly : I; assign x[7:2] = 0; From 3ee95542b8f7d9603cfffc06826ce6d54a5b431e Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 26 Nov 2019 12:25:51 +0100 Subject: [PATCH 16/20] Enabled 035b in Makefile Signed-off-by: Maciej Kurc --- fuzzers/035-iob-ilogic/Makefile | 9 +++++++-- fuzzers/035b-iob-iserdes/Makefile | 10 +++++++--- fuzzers/Makefile | 1 + 3 files changed, 15 insertions(+), 5 deletions(-) diff --git a/fuzzers/035-iob-ilogic/Makefile b/fuzzers/035-iob-ilogic/Makefile index e0e708a0..e6a26e88 100644 --- a/fuzzers/035-iob-ilogic/Makefile +++ b/fuzzers/035-iob-ilogic/Makefile @@ -10,8 +10,13 @@ include ../fuzzer.mk database: build/segbits_xioi3.db -build/segbits_xioi3.rdb: $(SPECIMENS_OK) - ${XRAY_SEGMATCH} -c 6 -o build/segbits_xioi3.rdb $$(find -name segdata_*) +build/segbits_xioi3.rdb2: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -c 6 -o build/segbits_xioi3.rdb2 $$(find -name segdata_*) + +build/segbits_xioi3.rdb: build/segbits_xioi3.rdb2 + # Filter out ISERDES features. Also filter DYN_CLK_INV_EN as they should + # belong to ISEDRES and are solved by fuzzer 035b. + grep -v ".ISERDES." $^ | grep -v "DYN_" >$@ build/segbits_xioi3.db: build/segbits_xioi3.rdb ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@ diff --git a/fuzzers/035b-iob-iserdes/Makefile b/fuzzers/035b-iob-iserdes/Makefile index 1bc5957e..784dc9d6 100644 --- a/fuzzers/035b-iob-iserdes/Makefile +++ b/fuzzers/035b-iob-iserdes/Makefile @@ -1,10 +1,14 @@ -N := 60 +N := 50 include ../fuzzer.mk database: build/segbits_xiob33.db -build/segbits_xiob33.rdb: $(SPECIMENS_OK) - ${XRAY_SEGMATCH} -c 20 -m 1 -M 1 -o build/segbits_xiob33.rdb $$(find -name segdata_*.txt) +build/segbits_xiob33.rdb2: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -c 20 -m 1 -M 1 -o build/segbits_xiob33.rdb2 $$(find -name segdata_*.txt) + +build/segbits_xiob33.rdb: build/segbits_xiob33.rdb2 + # Keep only solution for ISERDES related features. + grep -e ".ISERDES." $^ >$@ build/segbits_xiob33.db: build/segbits_xiob33.rdb ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@ diff --git a/fuzzers/Makefile b/fuzzers/Makefile index c09f6b23..a882cdfa 100644 --- a/fuzzers/Makefile +++ b/fuzzers/Makefile @@ -117,6 +117,7 @@ $(eval $(call fuzzer,032-cmt-pll,005-tilegrid,all)) $(eval $(call fuzzer,034-cmt-pll-pips,005-tilegrid 071-ppips,all)) $(eval $(call fuzzer,035-iob-ilogic,005-tilegrid,all)) $(eval $(call fuzzer,035a-iob-idelay,005-tilegrid,all)) +$(eval $(call fuzzer,035b-iob-iserdes,005-tilegrid,all)) $(eval $(call fuzzer,036-iob-ologic,005-tilegrid,all)) $(eval $(call fuzzer,037-iob-pips,005-tilegrid,all)) $(eval $(call fuzzer,038-cfg,005-tilegrid,all)) From 6396c941afd4f67e63e16919bafb9e8890cb545b Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 26 Nov 2019 16:16:16 +0100 Subject: [PATCH 17/20] Fixed fuzzer dependency. Signed-off-by: Maciej Kurc --- fuzzers/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fuzzers/Makefile b/fuzzers/Makefile index a882cdfa..794e430d 100644 --- a/fuzzers/Makefile +++ b/fuzzers/Makefile @@ -119,7 +119,7 @@ $(eval $(call fuzzer,035-iob-ilogic,005-tilegrid,all)) $(eval $(call fuzzer,035a-iob-idelay,005-tilegrid,all)) $(eval $(call fuzzer,035b-iob-iserdes,005-tilegrid,all)) $(eval $(call fuzzer,036-iob-ologic,005-tilegrid,all)) -$(eval $(call fuzzer,037-iob-pips,005-tilegrid,all)) +$(eval $(call fuzzer,037-iob-pips,005-tilegrid 035b-iob-iserdes,all)) $(eval $(call fuzzer,038-cfg,005-tilegrid,all)) $(eval $(call fuzzer,039-hclk-config,005-tilegrid,all)) $(eval $(call fuzzer,040-clk-hrow-config,005-tilegrid,all)) From 64b2075485d56e7a2b03e8480e8b7dc0dd71cb66 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 17 Jul 2020 12:48:34 +0200 Subject: [PATCH 18/20] Fixes 035b feature prefixes, added tag grouping Signed-off-by: Maciej Kurc --- fuzzers/035-iob-ilogic/Makefile | 2 +- fuzzers/035-iob-ilogic/tag_groups.txt | 13 +++++++++++ fuzzers/035b-iob-iserdes/Makefile | 30 ++++++++++++++++--------- fuzzers/035b-iob-iserdes/bits.dbf | 10 --------- fuzzers/035b-iob-iserdes/tag_groups.txt | 11 +++++++++ fuzzers/035b-iob-iserdes/top.py | 2 +- 6 files changed, 45 insertions(+), 23 deletions(-) create mode 100644 fuzzers/035-iob-ilogic/tag_groups.txt create mode 100644 fuzzers/035b-iob-iserdes/tag_groups.txt diff --git a/fuzzers/035-iob-ilogic/Makefile b/fuzzers/035-iob-ilogic/Makefile index e6a26e88..39842133 100644 --- a/fuzzers/035-iob-ilogic/Makefile +++ b/fuzzers/035-iob-ilogic/Makefile @@ -19,7 +19,7 @@ build/segbits_xioi3.rdb: build/segbits_xioi3.rdb2 grep -v ".ISERDES." $^ | grep -v "DYN_" >$@ build/segbits_xioi3.db: build/segbits_xioi3.rdb - ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@ + ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --groups tag_groups.txt --seg-fn-in $^ --seg-fn-out $@ ${XRAY_MASKMERGE} build/mask_xioi3.db $$(find -name segdata_*) pushdb: diff --git a/fuzzers/035-iob-ilogic/tag_groups.txt b/fuzzers/035-iob-ilogic/tag_groups.txt new file mode 100644 index 00000000..d4525fbd --- /dev/null +++ b/fuzzers/035-iob-ilogic/tag_groups.txt @@ -0,0 +1,13 @@ +IOI3.ILOGIC_Y0.IDELMUXE3.P0 IOI3.ILOGIC_Y0.IDELMUXE3.P1 + +IOI3.ILOGIC_Y0.IFF.SRTYPE.ASYNC IOI3.ILOGIC_Y0.IFF.SRTYPE.SYNC + +IOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE IOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE + +IOI3.ILOGIC_Y1.IDELMUXE3.P0 IOI3.ILOGIC_Y1.IDELMUXE3.P1 + +IOI3.ILOGIC_Y1.IFF.SRTYPE.ASYNC IOI3.ILOGIC_Y1.IFF.SRTYPE.SYNC + +IOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE IOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE + + diff --git a/fuzzers/035b-iob-iserdes/Makefile b/fuzzers/035b-iob-iserdes/Makefile index 784dc9d6..80d386fb 100644 --- a/fuzzers/035b-iob-iserdes/Makefile +++ b/fuzzers/035b-iob-iserdes/Makefile @@ -1,24 +1,32 @@ N := 50 include ../fuzzer.mk -database: build/segbits_xiob33.db +database: build/segbits_xioi3.db -build/segbits_xiob33.rdb2: $(SPECIMENS_OK) - ${XRAY_SEGMATCH} -c 20 -m 1 -M 1 -o build/segbits_xiob33.rdb2 $$(find -name segdata_*.txt) +build/segbits_xioi3.rdb2: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -c 20 -m 1 -M 1 -o build/segbits_xioi3.rdb2 $$(find -name segdata_*.txt) -build/segbits_xiob33.rdb: build/segbits_xiob33.rdb2 +build/segbits_xioi3.rdb: build/segbits_xioi3.rdb2 # Keep only solution for ISERDES related features. grep -e ".ISERDES." $^ >$@ -build/segbits_xiob33.db: build/segbits_xiob33.rdb - ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@ - ${XRAY_MASKMERGE} build/mask_xiob33.db $$(find -name segdata_*.txt) +build/segbits_xioi3.db: build/segbits_xioi3.rdb + ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --groups tag_groups.txt --seg-fn-in $^ --seg-fn-out $@ + ${XRAY_MASKMERGE} build/mask_xioi3.db $$(find -name segdata_*.txt) pushdb: - ${XRAY_MERGEDB} liob33 build/segbits_xiob33.db - ${XRAY_MERGEDB} riob33 build/segbits_xiob33.db - ${XRAY_MERGEDB} mask_liob33 build/mask_xiob33.db - ${XRAY_MERGEDB} mask_riob33 build/mask_xiob33.db + ${XRAY_MERGEDB} lioi3 build/segbits_xioi3.db + ${XRAY_MERGEDB} lioi3_tbytesrc build/segbits_xioi3.db + ${XRAY_MERGEDB} lioi3_tbyteterm build/segbits_xioi3.db + ${XRAY_MERGEDB} rioi3 build/segbits_xioi3.db + ${XRAY_MERGEDB} rioi3_tbytesrc build/segbits_xioi3.db + ${XRAY_MERGEDB} rioi3_tbyteterm build/segbits_xioi3.db + ${XRAY_MERGEDB} mask_lioi3 build/mask_xioi3.db + ${XRAY_MERGEDB} mask_lioi3_tbytesrc build/mask_xioi3.db + ${XRAY_MERGEDB} mask_lioi3_tbyteterm build/mask_xioi3.db + ${XRAY_MERGEDB} mask_rioi3 build/mask_xioi3.db + ${XRAY_MERGEDB} mask_rioi3_tbytesrc build/mask_xioi3.db + ${XRAY_MERGEDB} mask_rioi3_tbyteterm build/mask_xioi3.db .PHONY: database pushdb diff --git a/fuzzers/035b-iob-iserdes/bits.dbf b/fuzzers/035b-iob-iserdes/bits.dbf index 63a90990..820e8441 100644 --- a/fuzzers/035b-iob-iserdes/bits.dbf +++ b/fuzzers/035b-iob-iserdes/bits.dbf @@ -1,12 +1,2 @@ -IOI3.ILOGIC_Y0.IDELMUXE3.P0 ^ IOI3.ILOGIC_Y0.IDELMUXE3.P1 -IOI3.ILOGIC_Y0.IFFDELMUXE3.P0 ^ IOI3.ILOGIC_Y0.IFFDELMUXE3.P1 -IOI3.ILOGIC_Y1.IDELMUXE3.P0 ^ IOI3.ILOGIC_Y1.IDELMUXE3.P1 -IOI3.ILOGIC_Y1.IFFDELMUXE3.P0 ^ IOI3.ILOGIC_Y1.IFFDELMUXE3.P1 - -26_99 27_98 ,IOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE -26_99 27_98 ,IOI3.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE -26_29 27_28 ,IOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE -26_29 27_28 ,IOI3.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE - 26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112 26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26 diff --git a/fuzzers/035b-iob-iserdes/tag_groups.txt b/fuzzers/035b-iob-iserdes/tag_groups.txt new file mode 100644 index 00000000..c6461d82 --- /dev/null +++ b/fuzzers/035b-iob-iserdes/tag_groups.txt @@ -0,0 +1,11 @@ +IOI3.ILOGIC_Y0.ISERDES.MEMORY.DDR.4 IOI3.ILOGIC_Y0.ISERDES.MEMORY_DDR3.DDR.4 IOI3.ILOGIC_Y0.ISERDES.MEMORY_QDR.DDR.4 IOI3.ILOGIC_Y0.ISERDES.NETWORKING.DDR.10 IOI3.ILOGIC_Y0.ISERDES.NETWORKING.DDR.14 IOI3.ILOGIC_Y0.ISERDES.NETWORKING.DDR.4 IOI3.ILOGIC_Y0.ISERDES.NETWORKING.DDR.6 IOI3.ILOGIC_Y0.ISERDES.NETWORKING.DDR.8 IOI3.ILOGIC_Y0.ISERDES.NETWORKING.SDR.2 IOI3.ILOGIC_Y0.ISERDES.NETWORKING.SDR.3 IOI3.ILOGIC_Y0.ISERDES.NETWORKING.SDR.4 IOI3.ILOGIC_Y0.ISERDES.NETWORKING.SDR.5 IOI3.ILOGIC_Y0.ISERDES.NETWORKING.SDR.6 IOI3.ILOGIC_Y0.ISERDES.NETWORKING.SDR.7 IOI3.ILOGIC_Y0.ISERDES.NETWORKING.SDR.8 IOI3.ILOGIC_Y0.ISERDES.OVERSAMPLE.DDR.4 + +IOI3.ILOGIC_Y0.ISERDES.MODE.MASTER IOI3.ILOGIC_Y0.ISERDES.MODE.SLAVE + +IOI3.ILOGIC_Y0.ISERDES.NUM_CE.N1 IOI3.ILOGIC_Y0.ISERDES.NUM_CE.N2 + +IOI3.ILOGIC_Y1.ISERDES.MEMORY.DDR.4 IOI3.ILOGIC_Y1.ISERDES.MEMORY_DDR3.DDR.4 IOI3.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.4 IOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.10 IOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.14 IOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.4 IOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.6 IOI3.ILOGIC_Y1.ISERDES.NETWORKING.DDR.8 IOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.2 IOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.3 IOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.4 IOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.5 IOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.6 IOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.7 IOI3.ILOGIC_Y1.ISERDES.NETWORKING.SDR.8 IOI3.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.4 + +IOI3.ILOGIC_Y1.ISERDES.MODE.MASTER IOI3.ILOGIC_Y1.ISERDES.MODE.SLAVE + +IOI3.ILOGIC_Y1.ISERDES.NUM_CE.N1 IOI3.ILOGIC_Y1.ISERDES.NUM_CE.N2 diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index e1add6cb..cc61036a 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -14,7 +14,7 @@ from prjxray.db import Database def gen_sites(): - db = Database(util.get_db_root()) + db = Database(util.get_db_root(), util.get_part()) grid = db.grid() tile_list = [] From 144eda40e5be6be58e6fa2cf4368b57bbfd5f506 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 17 Jul 2020 13:05:09 +0200 Subject: [PATCH 19/20] Added licensing and encoding info Signed-off-by: Maciej Kurc --- fuzzers/035b-iob-iserdes/Makefile | 7 +++++++ fuzzers/035b-iob-iserdes/generate.py | 9 +++++++++ fuzzers/035b-iob-iserdes/generate.tcl | 7 +++++++ fuzzers/035b-iob-iserdes/top.py | 10 +++++++++- 4 files changed, 32 insertions(+), 1 deletion(-) diff --git a/fuzzers/035b-iob-iserdes/Makefile b/fuzzers/035b-iob-iserdes/Makefile index 80d386fb..443b22be 100644 --- a/fuzzers/035b-iob-iserdes/Makefile +++ b/fuzzers/035b-iob-iserdes/Makefile @@ -1,3 +1,10 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC N := 50 include ../fuzzer.mk diff --git a/fuzzers/035b-iob-iserdes/generate.py b/fuzzers/035b-iob-iserdes/generate.py index c2ac5e39..daa3469a 100644 --- a/fuzzers/035b-iob-iserdes/generate.py +++ b/fuzzers/035b-iob-iserdes/generate.py @@ -1,4 +1,13 @@ #!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC import json import re diff --git a/fuzzers/035b-iob-iserdes/generate.tcl b/fuzzers/035b-iob-iserdes/generate.tcl index c5751862..2765eba9 100644 --- a/fuzzers/035b-iob-iserdes/generate.tcl +++ b/fuzzers/035b-iob-iserdes/generate.tcl @@ -1,3 +1,10 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC set_param general.maxThreads 1 create_project -force -part $::env(XRAY_PART) design design diff --git a/fuzzers/035b-iob-iserdes/top.py b/fuzzers/035b-iob-iserdes/top.py index cc61036a..3e216ba7 100644 --- a/fuzzers/035b-iob-iserdes/top.py +++ b/fuzzers/035b-iob-iserdes/top.py @@ -1,5 +1,13 @@ #!/usr/bin/env python3 - +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC import os, random random.seed(int(os.getenv("SEED"), 16)) From 299e9dddde2c0e06a960fcc97efaa08782e1d7a5 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Mon, 20 Jul 2020 10:12:00 +0200 Subject: [PATCH 20/20] Cleaned up dbf files. Signed-off-by: Maciej Kurc --- fuzzers/035-iob-ilogic/bits.dbf | 2 -- fuzzers/035b-iob-iserdes/bits.dbf | 2 -- 2 files changed, 4 deletions(-) diff --git a/fuzzers/035-iob-ilogic/bits.dbf b/fuzzers/035-iob-ilogic/bits.dbf index 37275398..e69de29b 100644 --- a/fuzzers/035-iob-ilogic/bits.dbf +++ b/fuzzers/035-iob-ilogic/bits.dbf @@ -1,2 +0,0 @@ -27_110 27_112 26_109 ,IOB33.IOB_Y0.ISERDES.DATA_WIDTH.W2 -26_15 26_17 27_18 ,IOB33.IOB_Y1.ISERDES.DATA_WIDTH.W2 diff --git a/fuzzers/035b-iob-iserdes/bits.dbf b/fuzzers/035b-iob-iserdes/bits.dbf index 820e8441..e69de29b 100644 --- a/fuzzers/035b-iob-iserdes/bits.dbf +++ b/fuzzers/035b-iob-iserdes/bits.dbf @@ -1,2 +0,0 @@ -26_101 26_107 26_109 26_111 26_115 26_117 26_121 27_108 27_110 27_112 -26_15 26_17 26_19 27_6 27_10 27_12 27_16 27_18 27_20 27_26