From eaa9f05fbaad14923c5c5d4cc312b127f3da87f8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 8 Nov 2017 08:03:21 +0100 Subject: [PATCH] Add clbpips experiment Signed-off-by: Clifford Wolf Signed-off-by: Tim 'mithro' Ansell --- experiments/clbpips/.gitignore | 2 + experiments/clbpips/Makefile | 26 +++++++++ experiments/clbpips/generate.py | 22 ++++++++ experiments/clbpips/generate.sh | 11 ++++ experiments/clbpips/generate.tcl | 43 +++++++++++++++ experiments/clbpips/top.v | 92 ++++++++++++++++++++++++++++++++ 6 files changed, 196 insertions(+) create mode 100644 experiments/clbpips/.gitignore create mode 100644 experiments/clbpips/Makefile create mode 100644 experiments/clbpips/generate.py create mode 100644 experiments/clbpips/generate.sh create mode 100644 experiments/clbpips/generate.tcl create mode 100644 experiments/clbpips/top.v diff --git a/experiments/clbpips/.gitignore b/experiments/clbpips/.gitignore new file mode 100644 index 00000000..932efba0 --- /dev/null +++ b/experiments/clbpips/.gitignore @@ -0,0 +1,2 @@ +/specimen_[0-9][0-9][0-9]/ +/seg_clbl[lm].segbits diff --git a/experiments/clbpips/Makefile b/experiments/clbpips/Makefile new file mode 100644 index 00000000..d2111cbc --- /dev/null +++ b/experiments/clbpips/Makefile @@ -0,0 +1,26 @@ + +N := 5 +SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) +SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) + +database: database/clbll database/clblm + +pushdb: pushdb/clbll pushdb/clblm + +database/%: $(SPECIMENS_OK) + ../../tools/segmatch -o seg_$(notdir $@).segbits \ + $(addsuffix /segdata_$(notdir $@).txt,$(SPECIMENS)) + +pushdb/%: + bash ../../utils/mergedb.sh seg_$(notdir $@).segbits \ + ../../database/$(XRAY_DATABASE)/seg_$(notdir $@).segbits + +$(SPECIMENS_OK): + bash generate.sh $(subst /OK,,$@) + touch $@ + +clean: + rm -rf specimen_[0-9][0-9][0-9]/ seg_clbll.segbits seg_clblm.segbits + +.PHONY: database pushdb clean + diff --git a/experiments/clbpips/generate.py b/experiments/clbpips/generate.py new file mode 100644 index 00000000..faf1408a --- /dev/null +++ b/experiments/clbpips/generate.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 + +import sys, re + +sys.path.append("../../../utils/") +from segmaker import segmaker + +segmk = segmaker("design.bits") + +print("Loading tags from design.txt.") +with open("design.txt", "r") as f: + for line in f: + line, active = line.split() + tile, pip = line.split("/") + _, pip = pip.split(".") + + print(tile, pip, active) + segmk.addtag(tile, pip, int(active)) + +segmk.compile() +segmk.write() + diff --git a/experiments/clbpips/generate.sh b/experiments/clbpips/generate.sh new file mode 100644 index 00000000..81fce495 --- /dev/null +++ b/experiments/clbpips/generate.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +. ../../utils/genheader.sh + +echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh + +vivado -mode batch -source ../generate.tcl + +../../../tools/bitread -F $XRAY_ROI_FRAMES -o design.bits -zy design.bit +python3 ../generate.py + diff --git a/experiments/clbpips/generate.tcl b/experiments/clbpips/generate.tcl new file mode 100644 index 00000000..f242f1ae --- /dev/null +++ b/experiments/clbpips/generate.tcl @@ -0,0 +1,43 @@ +create_project -force -part $::env(XRAY_PART) design design + +read_verilog ../top.v +synth_design -top top + +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] + +set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \ + [get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical] + +create_pblock roi +add_cells_to_pblock [get_pblocks roi] [get_cells roi] +resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] + +place_design +route_design + +write_checkpoint -force design.dcp + +proc write_txtdata {filename} { + puts "Writing $filename." + set fp [open $filename w] + foreach tile [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] { + puts "Dumping pips from tile $tile" + foreach pip [get_pips -of_objects $tile] { + if {[get_nets -quiet -of_objects $pip] == {}} {puts $fp "$pip 0"} {puts $fp "$pip 1"} + } + } + close $fp +} + +write_bitstream -force design.bit +write_txtdata design.txt + diff --git a/experiments/clbpips/top.v b/experiments/clbpips/top.v new file mode 100644 index 00000000..b0619b4a --- /dev/null +++ b/experiments/clbpips/top.v @@ -0,0 +1,92 @@ +`include "setseed.vh" + +module top(input clk, stb, di, output do); + localparam integer DIN_N = 10; + localparam integer DOUT_N = 10; + + reg [DIN_N-1:0] din; + wire [DOUT_N-1:0] dout; + + reg [DIN_N-1:0] din_shr; + reg [DOUT_N-1:0] dout_shr; + + always @(posedge clk) begin + din_shr <= {din_shr, di}; + dout_shr <= {dout_shr, din_shr[DIN_N-1]}; + if (stb) begin + din <= din_shr; + dout_shr <= dout; + end + end + + assign do = dout_shr[DOUT_N-1]; + + roi roi ( + .clk(clk), + .din(din), + .dout(dout) + ); +endmodule + +module roi(input clk, input [9:0] din, output [9:0] dout); + localparam integer N = 200; + + function [31:0] xorshift32(input [31:0] v); + begin + xorshift32 = v; + xorshift32 = xorshift32 ^ (xorshift32 << 13); + xorshift32 = xorshift32 ^ (xorshift32 >> 17); + xorshift32 = xorshift32 ^ (xorshift32 << 5); + end + endfunction + + function [31:0] hash32(input [31:0] v); + begin + hash32 = v ^ `SEED; + hash32 = xorshift32(hash32); + hash32 = xorshift32(hash32); + hash32 = xorshift32(hash32); + hash32 = xorshift32(hash32); + end + endfunction + + function [63:0] hash64(input [31:0] v); + begin + hash64[63:32] = hash32(v); + hash64[31: 0] = hash32(~v); + end + endfunction + + wire [N*10+9:0] nets; + + assign nets[9:0] = din; + assign dout = nets[N*10+9:N*10]; + + genvar i, j; + generate + for (i = 0; i < N; i = i+1) begin:is + for (j = 0; j < 10; j = j+1) begin:js + localparam integer k = i*10 + j + 10; + wire lut_out; + + LUT6 #( + .INIT(hash64({i, j, 8'hff})) + ) lut ( + .I0(nets[hash32({i, j, 8'h00}) % k]), + .I1(nets[hash32({i, j, 8'h01}) % k]), + .I2(nets[k-10]), + .I3(nets[k-9]), + .I4(nets[k-8]), + .I5(nets[k-7]), + .O(lut_out) + ); + + reg lut_out_reg; + always @(posedge clk) + lut_out_reg <= lut_out; + + assign nets[k] = ((i+j) % 17) < 10 ? lut_out_reg : lut_out; + end + end + endgenerate +endmodule