From e9dbc39e9cde0ba5bdb50958a057c9a636394f5e Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 26 Jul 2019 17:48:22 -0700
Subject: [PATCH] Add HCLK_IOI3.INTERNAL_VREF feature.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fuzzers/030-iob/Makefile           | 10 ++++-
 fuzzers/030-iob/generate.py        | 69 ++++++++++++++++++++++++++++++
 fuzzers/030-iob/hclk_bits.dbf      |  0
 fuzzers/030-iob/top.py             |  2 +-
 fuzzers/030-iob/write_io_banks.tcl | 13 +++++-
 5 files changed, 91 insertions(+), 3 deletions(-)
 create mode 100644 fuzzers/030-iob/hclk_bits.dbf

diff --git a/fuzzers/030-iob/Makefile b/fuzzers/030-iob/Makefile
index 2867ac12..8f0a4e52 100644
--- a/fuzzers/030-iob/Makefile
+++ b/fuzzers/030-iob/Makefile
@@ -2,7 +2,7 @@ N := 50
 SPECIMENS_DEPS := build/iobanks.txt
 include ../fuzzer.mk
 
-database: build/segbits_xiob33.db
+database: build/segbits_xiob33.db build/segbits_hclk_ioi3.db
 
 build/iobanks.txt: write_io_banks.tcl
 	mkdir -p build
@@ -16,6 +16,12 @@ build/segbits_xiob33.db: build/segbits_xiob33.rdb process_rdb.py bits.dbf
 	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in build/segbits_xiob33_processed.rdb --seg-fn-out $@
 	${XRAY_MASKMERGE} build/mask_xiob33.db $$(find -name segdata_liob33.txt) $$(find -name segdata_riob33.txt)
 
+build/segbits_hclk_ioi3.rdb: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -o build/segbits_hclk_ioi3.rdb $$(find -name segdata_hclk_ioi3.txt)
+
+build/segbits_hclk_ioi3.db: build/segbits_hclk_ioi3.rdb
+	${XRAY_DBFIXUP} --db-root build --zero-db hclk_bits.dbf --seg-fn-in build/segbits_hclk_ioi3.rdb --seg-fn-out $@
+
 pushdb:
 ifneq (${XRAY_DATABASE}, zynq7)
 	${XRAY_MERGEDB} liob33 build/segbits_xiob33.db
@@ -24,5 +30,7 @@ endif
 	${XRAY_MERGEDB} riob33 build/segbits_xiob33.db
 	${XRAY_MERGEDB} mask_riob33 build/mask_xiob33.db
 
+	${XRAY_MERGEDB} hclk_ioi3 build/segbits_hclk_ioi3.db
+
 .PHONY: database pushdb
 
diff --git a/fuzzers/030-iob/generate.py b/fuzzers/030-iob/generate.py
index 82ecd66b..4ea131da 100644
--- a/fuzzers/030-iob/generate.py
+++ b/fuzzers/030-iob/generate.py
@@ -185,6 +185,75 @@ def main():
                 segmk.add_site_tag(
                     site, 'INTERMDISABLE.I', d['intermdisable_wire'] != '0')
 
+    # Create map of iobank -> sites
+    iobanks = {}
+    with open(os.path.join(os.getenv('FUZDIR'), 'build', 'iobanks.txt')) as f:
+        for l in f:
+            iob_site, iobank = l.strip().split(',')
+            iobank = int(iobank)
+
+            if iobank not in iobanks:
+                iobanks[iobank] = set()
+
+            iobanks[iobank].add(iob_site)
+
+    site_to_cmt = {}
+    site_to_tile = {}
+    tile_to_cmt = {}
+    cmt_to_idelay = {}
+    with open(os.path.join(os.getenv('FUZDIR'), 'build',
+                           'cmt_regions.csv')) as f:
+        for l in f:
+            site, tile, cmt = l.strip().split(',')
+            site_to_tile[site] = tile
+
+            site_to_cmt[site] = cmt
+            tile_to_cmt[tile] = cmt
+
+            # Given IDELAYCTRL's are only located in HCLK_IOI3 tiles, and
+            # there is only on HCLK_IOI3 tile per CMT, update
+            # CMT -> IDELAYCTRL / tile map.
+            if 'IDELAYCTRL' in site:
+                assert cmt not in cmt_to_idelay
+                cmt_to_idelay[cmt] = site, tile
+
+    # For each IOBANK with an active VREF set the feature
+    cmt_vref_active = set()
+    with open('iobank_vref.csv') as f:
+        for l in f:
+            iobank, vref = l.strip().split(',')
+            iobank = int(iobank)
+
+            cmt = None
+            for cmt_site in iobanks[iobank]:
+                if cmt_site in site_to_cmt:
+                    cmt = site_to_cmt[cmt_site]
+                    break
+
+            if cmt is None:
+                continue
+
+            cmt_vref_active.add(cmt)
+
+            _, hclk_cmt_tile = cmt_to_idelay[cmt]
+
+            opt = 'VREF.V_{:d}_MV'.format(int(float(vref) * 1000))
+            segmk.add_tile_tag(hclk_cmt_tile, opt, 1)
+
+    # For IOBANK's with no active VREF, clear all VREF options.
+    for cmt, (_, hclk_cmt_tile) in cmt_to_idelay.items():
+        if cmt in cmt_vref_active:
+            continue
+
+        for vref in (
+                .600,
+                .675,
+                .75,
+                .90,
+        ):
+            opt = 'VREF.V_{:d}_MV'.format(int(vref * 1000))
+            segmk.add_tile_tag(hclk_cmt_tile, opt, 0)
+
     segmk.compile(bitfilter=bitfilter)
     segmk.write(allow_empty=True)
 
diff --git a/fuzzers/030-iob/hclk_bits.dbf b/fuzzers/030-iob/hclk_bits.dbf
new file mode 100644
index 00000000..e69de29b
diff --git a/fuzzers/030-iob/top.py b/fuzzers/030-iob/top.py
index e7c59238..4e027f9f 100644
--- a/fuzzers/030-iob/top.py
+++ b/fuzzers/030-iob/top.py
@@ -100,7 +100,7 @@ def run():
     }
 
     with open(os.path.join(os.getenv('FUZDIR'), 'build', 'iobanks.txt')) as f:
-        iobanks = [int(l.strip()) for l in f]
+        iobanks = [int(l.strip().split(',')[1]) for l in f]
 
     params['iobanks'] = iobanks
 
diff --git a/fuzzers/030-iob/write_io_banks.tcl b/fuzzers/030-iob/write_io_banks.tcl
index 996928e7..8ed0427c 100644
--- a/fuzzers/030-iob/write_io_banks.tcl
+++ b/fuzzers/030-iob/write_io_banks.tcl
@@ -3,6 +3,17 @@ set_property design_mode PinPlanning [current_fileset]
 open_io_design -name io_1
 set fp [open "iobanks.txt" "w"]
 foreach iobank [get_iobanks] {
-    puts $fp $iobank
+    foreach site [get_sites -of $iobank] {
+        puts $fp "$site,$iobank"
+    }
+}
+close $fp
+
+set fp [open "cmt_regions.csv" "w"]
+foreach site_type { IOB33M IOB33S IDELAYCTRL} {
+    foreach site [get_sites -filter "SITE_TYPE == $site_type"] {
+        set tile [get_tiles -of $site]
+        puts $fp "$site,$tile,[get_property CLOCK_REGION $site]"
+    }
 }
 close $fp