From 22213404a555e1cf2a522e8d46f25c363608e060 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 24 Jan 2020 20:04:26 +0000 Subject: [PATCH] fuzzers: Improve DSP fuzzer Signed-off-by: David Shah --- fuzzers/100-dsp-mskpat/generate.py | 115 ++++++++++++++++++++--------- fuzzers/100-dsp-mskpat/top.py | 16 ++-- 2 files changed, 91 insertions(+), 40 deletions(-) diff --git a/fuzzers/100-dsp-mskpat/generate.py b/fuzzers/100-dsp-mskpat/generate.py index fe0d3271..3dea122b 100644 --- a/fuzzers/100-dsp-mskpat/generate.py +++ b/fuzzers/100-dsp-mskpat/generate.py @@ -1,13 +1,14 @@ #!/usr/bin/env python3 -from prjxray.segmaker import Segmaker +from prjxray.segmaker import Segmaker, add_site_group_zero from prjxray.verilog import to_int from prjxray.verilog import quote import json -def add(segmk, site, dsp, tag, bit, value, invert): - tag = "%s.%s%s[%u]" % (dsp, ('Z' if invert else ''), tag, bit) +def add(segmk, site, dsp, tag, bit, value, invert, is_vector=True): + tag = "%s.%s%s%s" % ( + dsp, ('Z' if invert else ''), tag, '[%u]' % bit if is_vector else '') value = (~value if invert else value) value >>= bit return segmk.add_site_tag(site, tag, value & 1) @@ -20,32 +21,65 @@ def run(): with open('params.json', 'r') as fp: data = json.load(fp) + used_dsps = set() + for params in data['instances']: dsp = "DSP_0" if params['SITE'][-1] in "02468" else "DSP_1" site = params['SITE'] - add(segmk, site, dsp, 'ADREG', 0, to_int(params['ADREG']), 0) + if params['USE_DPORT'] == quote( + "TRUE") and params['USE_MULT'] != quote("NONE"): + add(segmk, site, dsp, 'ADREG', 0, to_int(params['ADREG']), 1) add(segmk, site, dsp, 'ALUMODEREG', 0, to_int(params['ALUMODEREG']), 1) - for i in range(2): - add(segmk, site, dsp, 'AREG', i, to_int(params['AREG']), 1) + if params['A_INPUT'] == quote("DIRECT"): + add( + segmk, site, dsp, 'AREG_0', 0, + int(to_int(params['AREG']) == 0), 0, False) + add( + segmk, site, dsp, 'AREG_2', 0, + int(to_int(params['AREG']) == 2), 0, False) - for i in range(2): - add(segmk, site, dsp, 'ACASCREG', i, to_int(params['ACASCREG']), 1) + if params['B_INPUT'] == quote("DIRECT"): + add( + segmk, site, dsp, 'BREG_0', 0, + int(to_int(params['BREG']) == 0), 0, False) + add( + segmk, site, dsp, 'BREG_2', 0, + int(to_int(params['BREG']) == 2), 0, False) - for i in range(2): - add(segmk, site, dsp, 'BREG', i, to_int(params['BREG']), 1) + if params['A_INPUT'] == quote("CASCADE"): + add( + segmk, site, dsp, 'AREG_2_ACASCREG_1', 0, + int( + to_int(params['AREG']) == 2 + and to_int(params['ACASCREG']) == 1), 0, False) + add( + segmk, site, dsp, 'AREG_2_ACASCREG_1', 0, + int( + to_int(params['AREG']) == 2 + and to_int(params['ACASCREG']) == 1), 1, False) - for i in range(2): - add(segmk, site, dsp, 'BCASCREG', i, to_int(params['BCASCREG']), 1) + if params['B_INPUT'] == quote("CASCADE"): + add( + segmk, site, dsp, 'BREG_2_BCASCREG_1', 0, + int( + to_int(params['BREG']) == 2 + and to_int(params['BCASCREG']) == 1), 0, False) + add( + segmk, site, dsp, 'BREG_2_BCASCREG_1', 0, + int( + to_int(params['BREG']) == 2 + and to_int(params['BCASCREG']) == 1), 1, False) add(segmk, site, dsp, 'CARRYINREG', 0, to_int(params['CARRYINREG']), 1) add( segmk, site, dsp, 'CARRYINSELREG', 0, to_int(params['CARRYINSELREG']), 1) add(segmk, site, dsp, 'CREG', 0, to_int(params['CREG']), 1) - - add(segmk, site, dsp, 'DREG', 0, to_int(params['DREG']), 0) + if params['USE_DPORT'] == quote( + "TRUE") and params['USE_MULT'] != quote("NONE"): + add(segmk, site, dsp, 'DREG', 0, to_int(params['DREG']), 1) add(segmk, site, dsp, 'INMODEREG', 0, to_int(params['INMODEREG']), 1) add(segmk, site, dsp, 'OPMODEREG', 0, to_int(params['OPMODEREG']), 1) add(segmk, site, dsp, 'PREG', 0, to_int(params['PREG']), 1) @@ -63,13 +97,12 @@ def run(): add(segmk, site, dsp, 'USE_DPORT', 0, BOOL[params['USE_DPORT']], 0) - SIMD = {} - SIMD[quote('ONE48')] = 0 - SIMD[quote('TWO24')] = 1 - SIMD[quote('FOUR12')] = 2 - - for i in range(2): - add(segmk, site, dsp, 'USE_SIMD', i, SIMD[params['USE_SIMD']], 0) + add( + segmk, site, dsp, 'USE_SIMD_FOUR12', 0, + params['USE_SIMD'] == quote("FOUR12"), 0, False) + add( + segmk, site, dsp, 'USE_SIMD_FOUR12_TWO24', 0, + params['USE_SIMD'] in (quote("TWO24"), quote("FOUR12")), 0, False) MULT = {} MULT[quote('NONE')] = 0 @@ -87,11 +120,12 @@ def run(): AUTORESET[quote('RESET_MATCH')] = 2 add( - segmk, site, dsp, 'AUTORESET_PATDET', 0, - AUTORESET[params['AUTORESET_PATDET']], 0) + segmk, site, dsp, 'AUTORESET_PATDET_RESET_NOT_MATCH', 0, + params['AUTORESET_PATDET'] == quote("RESET_NOT_MATCH"), 0, False) add( - segmk, site, dsp, 'AUTORESET_PATDET', 1, - AUTORESET[params['AUTORESET_PATDET']], 1) + segmk, site, dsp, 'AUTORESET_PATDET_RESET', 0, + params['AUTORESET_PATDET'] in ( + quote("RESET_NOT_MATCH"), quote("RESET_MATCH")), 0, False) for i in range(48): add(segmk, site, dsp, 'MASK', i, to_int(params['MASK']), 0) @@ -99,16 +133,12 @@ def run(): for i in range(48): add(segmk, site, dsp, 'PATTERN', i, to_int(params['PATTERN']), 0) - SEL_MASK = {} - SEL_MASK[quote('MASK')] = 0 - SEL_MASK[quote('C')] = 1 - SEL_MASK[quote('ROUNDING_MODE1')] = 2 - SEL_MASK[quote('ROUNDING_MODE2')] = 3 - - for i in range(2): - add( - segmk, site, dsp, 'SEL_MASK', i, SEL_MASK[params['SEL_MASK']], - 0) + if params['USE_PATTERN_DETECT'] == quote("PATDET"): + add_site_group_zero( + segmk, site, dsp + ".", [ + "SEL_MASK_%s" % x + for x in ["MASK", "C", "ROUNDING_MODE1", "ROUNDING_MODE2"] + ], "SEL_MASK_MASK", "SEL_MASK_%s" % (params['SEL_MASK'][1:-1])) USE_PATTERN_DETECT = {} USE_PATTERN_DETECT[quote('NO_PATDET')] = 0 @@ -118,6 +148,21 @@ def run(): segmk, site, dsp, 'USE_PATTERN_DETECT', 0, USE_PATTERN_DETECT[params['USE_PATTERN_DETECT']], 0) + inv_ports = [ + ("ALUMODE", 4), + ("CARRYIN", 1), + ("CLK", 1), + ("INMODE", 5), + ("OPMODE", 7), + ] + + for port, width in inv_ports: + param = 'IS_{}_INVERTED'.format(port) + for i in range(width): + add( + segmk, site, dsp, param, i, to_int(params[param]), 1, + width > 1) + segmk.compile() segmk.write() diff --git a/fuzzers/100-dsp-mskpat/top.py b/fuzzers/100-dsp-mskpat/top.py index a480ebb6..020d0282 100644 --- a/fuzzers/100-dsp-mskpat/top.py +++ b/fuzzers/100-dsp-mskpat/top.py @@ -49,14 +49,14 @@ def run(): ports['A'] = '{30{1\'b1}}' ports['ACIN'] = '{30{1\'b1}}' ports['ACOUT'] = '30\'b0' - ports['ALUMODE'] = '4\'b1' + ports['ALUMODE'] = 'din[3:0]' ports['B'] = '{18{1\'b1}}' ports['BCIN'] = '{18{1\'b1}}' ports['BCOUT'] = '18\'b0' ports['C'] = '{48{1\'b1}}' ports['CARRYCASCIN'] = '1\'b1' ports['CARRYCASCOUT'] = '1\'b0' - ports['CARRYIN'] = '1\'b1' + ports['CARRYIN'] = 'din[4]' ports['CARRYINSEL'] = '3\'b000' ports['CARRYOUT'] = '4\'b0' ports['CEA1'] = '1\'b1' @@ -72,12 +72,12 @@ def run(): ports['CEINMODE'] = '1\'b1' ports['CEM'] = '1\'b1' ports['CEP'] = '1\'b1' - ports['CLK'] = '1\'b1' + ports['CLK'] = 'clk' ports['D'] = '{25{1\'b1}}' - ports['INMODE'] = '5\'b11111' + ports['INMODE'] = 'din[9:5]' #ports['MULTISIGNIN'] = '1\'b1' #ports['MULTISIGNOUT'] = '1\'b0' - ports['OPMODE'] = '7\'b1111111' + ports['OPMODE'] = 'din[16:10]' ports['OVERFLOW'] = '1\'b0' ports['P'] = '48\'b0' ports['PATTERNBDETECT'] = '1\'b0' @@ -133,6 +133,12 @@ def run(): params['USE_PATTERN_DETECT'] = verilog.quote( fuzz(('NO_PATDET', 'PATDET'))) + params['IS_ALUMODE_INVERTED'] = fuzz(4) + params['IS_CARRYIN_INVERTED'] = fuzz((0, 1)) + params['IS_CLK_INVERTED'] = fuzz((0, 1)) + params['IS_INMODE_INVERTED'] = fuzz(5) + params['IS_OPMODE_INVERTED'] = fuzz(7) + verilog.instance(synthesis + ' ' + module, instance, ports, params) params['TILE'] = tile